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freescale semiconductor data sheet: technical data document number: pxr40 rev. 1, 09/2011 ? freescale semiconductor, inc., 2011. all rights reserved. pxr40 tepbga?416 27mm x 27mm ? dual issue, 32-bit cpu core complex (e200z7) ? compliant with the powe r architecture embedded category ? 16 kb i-cache and 16 kb d-cache ? includes an instruction set enhancement allowing variable length encoding (vle), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction ? includes signal processing extension (spe2) instruction support for digital signal processing (dsp) and single-precision floating point operations ? 4 mb on-chip flash ? supports read during program and erase operations, and multiple blocks allowing eeprom emulation ? 256 kb on-chip general-purpose sram including 32 kb of standby ram ? two direct memory access controller (edma2) blocks ? one supporting 64 channels ? one supporting 32 channels ? interrupt controller (intc) ? frequency modulated phase-locked loop (fmpll) ? crossbar switch architecture for concurrent access to peripherals, flash, or ram from multiple bus masters ? external bus interface (ebi) fo r calibration and application development (not availa ble on all packages) ? system integration unit (siu) ? error correction status module (ecsm) ? boot assist module (bam) supports serial bootload via can or sci ? two second-generation enha nced time processor units (etpu2) that share code and data ram. ? 32 standard channels per etpu2 ? 24 kb code ram ? 6 kb parameter (data) ram ? enhanced modular input output system supporting 32 unified channels (e mios) with each channel capable of single action, double action, pulse width modulation (pwm) and modulus counter operation ? four enhanced queued anal og-to-digital converters (eqadc) ? support for 64 analog channels ? includes one absolute reference adc channel ? includes eight decimation filters ? four deserial serial peri pheral interf ace (spi) modules ? three enhanced serial communication interface (uart) modules ? four controller area network (can) modules ? dual-channel flexray controller ? nexus development inte rface (ndi) per ieee-isto 5001-2003/5001-2008 standard ? device and board test support per joint test action group (jtag) (ieee 1149.1) ? on-chip voltage regulator controller regulates supply voltage down to 1.2 v for core logic pxr40 microcontroller data sheet
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 2 table of contents 1 pxr40 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 pxr40 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1 416-ball tepbga pin assignments. . . . . . . . . . . . . . . . .6 4 signal properties and muxing . . . . . . . . . . . . . . . . . . . . . . . . .11 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.1 maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.2 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .53 5.2.1 general notes for specifications at maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3 emi (electromagnetic interfer ence) characteristics . . .55 5.4 esd characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5.5 pmc/por/lvi electrical specifications . . . . . . . . . . . . .56 5.6 power up/down sequencing . . . . . . . . . . . . . . . . . . . . .59 5.6.1 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.6.2 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.6.3 power sequencing and por dependent on v dda 60 5.7 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . .61 5.7.1 i/o pad current specifications . . . . . . . . . . . . . .64 5.7.2 i/o pad v dd33 current specifications . . . . . . . . .64 5.7.3 lvds pad specifications . . . . . . . . . . . . . . . . . .65 5.8 oscillator and fmpll electrical characteristics . . . . . .66 5.9 eqadc electrical characteristics . . . . . . . . . . . . . . . . . 68 5.9.1 adc internal resource measurements . . . . . . . 69 5.10 c90 flash memory electrical characteristics . . . . . . . . 71 5.11 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.11.1 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.11.2 pad ac specifications. . . . . . . . . . . . . . . . . . . . 74 5.12 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.12.1 generic timing diagrams . . . . . . . . . . . . . . . . . 77 5.12.2 reset and configuration pin timing . . . . . . . . . . 78 5.12.3 ieee 1149.1 interface timing . . . . . . . . . . . . . . 78 5.12.4 nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.12.5 external bus interface (ebi) timing . . . . . . . . . 84 5.12.6 external interrupt timing (irq pin) . . . . . . . . . . 88 5.12.7 etpu timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.12.8 emios timing . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.12.9 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.1 416-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8 product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
pxr40 features pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 3 1 pxr40 features table 1 displays the pxr40 feature set. table 1. pxr40 feature set feature pxr40 core e200z7 simd yes vle yes cache 32 kb (16 kb instruction/16 kb data) non-maskable interrupt (nmi) n mi & critical interrupt mmu 64 entry mpu yes xbar 5 5 windowing software watchdog yes nexus 3+ sram 256 kb flash 4 mb flash fetch accelerator 4 256 bit (first 1 mb of memory is 4 128; last 3 mb are 4 256) external bus yes calibration bus 16 bit non-muxed 32 bit muxed dma 96 channel dma nexus class 3 serial 3 uart_a yes uart_b yes uart_c yes microsecond bus uplink yes can 4 can_a 64 message buffers can_b 64 message buffers can_c 64 message buffers can_d 64 message buffers can_e no spi 4 spi_a yes spi_b yes spi_c yes spi_d yes flexray yes ethernet no system timers 4 pit chan 4 swt 1 watchdog emios 32 channel etpu 64 channel etpu_a yes (etpu2) etpu_b yes (etpu2)
pxr40 microcontroller data sheet, rev. 1 pxr40 features freescale semiconductor 4 note: 3.3 v is required for certain io segments only du ring debug/development (e.g., nexus 3 trace and bus) code memory 24 kb data memory 6 kb interrupt controller 448 adc 64 channel eqadc_a yes eqadc_b yes temperature sensor yes variable gain amp. yes decimation filter yes (8 on eqadc_b) sensor diagnostics yes pll fm vrc yes supplies 5v low power modes stop mode slow mode table 1. pxr40 feature set (continued) feature pxr40
pxr40 block diagram pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 5 2 pxr40 block diagram figure 1 shows a top-level block diagram of the pxr40 microcontrollers. figure 1. block diagram crossbar switch (xbar) memory protection unit (mpu) data and instruction system pbridge a pxr40 block diagram system integration interrupt controller osc/pll spe2 debug nexus jtag ieee isto 5001?-2003 2 x edma 64- and 32-ch e200z7 superscalar cpu pbridge b 256 kb sram w/ecc (32 kb s/b) 4mb flash w/ecc main memory system siu timed i/o system boot assist module (bam) 6k data 24k code ram emios 32-ch etpu2 32-ch etpu2 32-ch 4 x can 3 x uart/ 4 x spi 4 x dec fil 64-ch quad adci communications flexray? controller adc ? analog-to-digital converter adci ? adc interface aips ? peripheral i/o bridge amux ? analog multiplexer can ? controller area network decfil ? decimation filter ebi ? external bus interface ecsm ? error correction status module edma2 ? enhanced direct memory access emios ? enhanced modular i/o system eqadc ? enhanced queued a/d converter module etpu2 ? enhanced time processing unit 2 mmu ? memory management unit mpu ? memory protection unit pbridge ? peripheral i/o bridge s/b ? stand-by siu ? system integration unit spe2 ? signal processing engine 2 spi ? serial peripheral interface controller sram ? general-purpose static ram uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network vle ? variable length instruction encoding lin
pxr40 microcontroller data sheet, rev. 1 pin assignments freescale semiconductor 6 3 pin assignments the figures in this section show the primary pin functi on. for the full signal proper ties and muxing table, see table 4 . 3.1 416-ball tepbga pin assignments figure 2 shows the 416-ball tepbga pin assignments in one figure. the same information is shown in figure 3 through figure 6 . figure 2. pxr40 416-ball tepbga (full diagram) vssfl regctl etpub26 tdo mdo15 vdde2 vdde2 vdde2 vss 12345678910111213141516 vdd rstout ana0 ana15 vdda_a0 vrh_a an28 an32 an36 vdda_b0 a vddeh1 vss vdd test ana1 ana5 ana14 vdda_a1 ref? an24 an27 an29 an33 vdda_b1 b vss vdd ana2 ana6 ana13 ana17 ana19 ana21 ana23 an26 an30 an34 an37 c vss vdd ana3 ana12 ana18 ana20 an25 an31 an35 an39 d e f g vss vss vss vss vss vss vss vss vss vss vss vss h vss vdde2 vss vss j k l m vss vdde2 vdd ac vss fr_a_ emios5 ad vss fr_a_ emios6 ae vss vdde2 emios7 af ana7 ana9 ana4 pxr40 416-ball tepbga (as viewed from top through the package) vrl_a vssa_a1 pcsa1 fr_a_ ana11 ana8 etpua30 ana16 vdd pcsa5 ana10 ana22 vddeh4 vddeh3 pcsb1 pcsb4 pcsa2 etpua2 vstby rxda txda vdd33_1 vdd tdi vdde2 vdd engclk fr_b_ emios2 pcsb3 scka souta pcsb0 fr_b_ pcsa0 pcsa4 emios3 emios0 sckb pcsa3 sinb fr_b_ pcsb5 vddeh3 emios4 emios1 pcsb2 sina soutb 17 18 19 20 21 22 23 24 25 26 vrl_b vrh_b anb14 anb17 anb21 anb23 vss ref? anb6 anb10 anb15 anb18 anb22 vss anb0 anb4 anb5 anb12 anb16 anb19 vss anb2 anb9 anb13 vss vddeh7 vddeh7 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss pcsc1 vss rxdc pcsc3 vss vdd vddsyn sinc pcsc2 pcsc5 vss vddeh4 txdc vss a b c d e f g h j k l m anb1 an38 anb11 anb7 anb8 anb3 xtal vddeh5 vssa_b0 anb20 etpuc7 etpub15 etpub14 vddeh7 vdd vddeh6 vddeh5 cnrxd cnrxb sckc cntxd cntxb pcsc0 cnrxc cnrxa soutc cntxc cntxa pcsc4 vdd 1234567891011121314151617181920212223242526 wkpcfg vdd n vddeh1 p r t u v w y aa ab pllcfg2 rdy rxdb txdb pllcfg0 evti reset jcomp mseo1 mcko vdde2 mdo1 mdo0 mseo0 evto mdo5 mdo4 mdo3 mdo2 vdde2 mdo8 mdo7 mdo6 mdo11 mdo10 mdo9 vdd33_2 mdo14 mdo13 mdo12 vdd tms tck vddeh6 etpub11 etpub12 etpub13 etpub7 etpub8 etpub9 etpub10 etpub3 etpub4 etpub5 etpub0 etpub1 etpub2 etpub19 etpub20 regsel etpub25 etpub24 etpub23 etpub29 etpub28 etpub27 vdd33_3 etpub30 vsssyn vdd n p r t u v w y aa ab etpub18 etpub17 etpub16 etpub21 etpub22 tcrclkb vddreg etpub31 extal vss vdde2 vss vss vdde2 vss vss vdde2 vss vdde2 vdde2 vdde2 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss ac ad ae af etpua27 etpua23 etpua19 etpua15 etpua11 etpua7 etpua3 tcrclka etpua28 etpua24 etpua20 etpua16 etpua12 etpua8 etpua4 etpua31 etpua29 etpua25 etpua21 etpua17 etpua14 etpua9 etpua5 etpua1 etpua26 etpua22 etpua18 etpua13 etpua10 etpua6 emios8 emios9 emios10 emios11 emios14 emios15 emios13 emios12 emios18 emios19 emios17 emios16 emios22 emios23 emios21 emios20 emios27 emios26 emios25 emios24 emios31 emios30 emios29 emios28 rx tx_en tx_en rx tx tx bypca bypcb etpuc11 etpuc15 etpuc19 etpuc23 etpuc27 etpuc31 etpuc8 etpuc12 etpuc16 etpuc20 etpuc24 etpuc28 etpuc9 etpuc13 etpuc17 etpuc21 etpuc25 etpuc29 etpuc10 etpuc14 etpuc18 etpuc22 etpuc26 etpuc30 etpuc4 etpuc5 etpuc6 etpuc3 etpuc1 tcrclkc etpuc2 etpuc0 etpub6 etpua0 vdde2 boot? cfg1 pllcfg1 ref? bypca1 ref? bypcb1
pin assignments pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 7 figure 3. pxr40 416-ball tepbga (1 of 4) 12345678910111213 12345678910111213 vdd vss txda bootcfg1 etpua28 etpua24 etpua20 etpua16 etpua12 etpua8 etpua4 etpua0 vss rstout ana0 ana15 vdda_a0 vrh_a an28 vddeh1 vdd test ana1 ana5 ana14 vdda_a1 refbypca an24 an27 vss vdd ana2 ana6 ana13 ana17 ana19 ana21 ana23 an26 vss vdd ana3 ana12 ana18 ana20 an25 vss vss vss vss vss vss vss vss vss vss vss vss vss vdde2 vss vss ana7 ana9 ana4 vrl_a vssa_a1 ana11 ana8 etpua30 ana16 ana10 ana22 etpua2 vstby rxda vdd33_1 wkpcfg vdd rxdb etpua27 etpua23 etpua19 etpua15 etpua11 etpua7 etpua3 tcrclka etpua31 etpua29 etpua25 etpua21 etpua17 etpua14 etpua9 etpua5 etpua1 etpua26 etpua22 etpua18 etpua13 etpua10 etpua6 a b e f g h j k l m n c d a b e f g h j k l m n c d pxr40 416-ball tepbga (as viewed from top through the package) (1 of 4) refbyp- ca1
pxr40 microcontroller data sheet, rev. 1 pin assignments freescale semiconductor 8 figure 4. pxr40 416-ball tepbga (2 of 4) 14 15 16 17 18 19 20 21 22 23 24 25 26 14 15 16 17 18 19 20 21 22 23 24 25 26 an32 an36 vdda_b0 an29 an33 vdda_b1 an30 an34 an37 an31 an35 an39 vrl_b vrh_b anb14 anb17 anb21 anb23 vss refbypcb anb6 anb10 anb15 anb18 anb22 vss anb0 anb4 anb5 anb12 anb16 anb19 vss anb2 anb9 anb13 vss vddeh7 vddeh7 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss anb1 an38 anb11 anb7 anb8 anb3 vssa_b0 anb20 etpuc7 etpub15 etpub14 vddeh7 vddeh6 etpub11 etpub12 etpub13 etpuc11 etpuc15 etpuc19 etpuc23 etpuc27 etpuc31 etpuc8 etpuc12 etpuc16 etpuc20 etpuc24 etpuc28 etpuc9 etpuc13 etpuc17 etpuc21 etpuc25 etpuc29 etpuc10 etpuc14 etpuc18 etpuc22 etpuc26 etpuc30 etpuc4 etpuc5 etpuc6 etpuc3 etpuc1 tcrclkc etpuc2 etpuc0 a b e f g h j k l m n c d a b e f g h j k l m n c d pxr40 416-ba ll tepbga (as viewed from top through the package) (2 of 4) refbyp- cb1
pin assignments pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 9 figure 5. pxr40 416-ball tepbga (3 of 4) vdde2 vdde2 tdo mdo15 p r v w y aa ab ac ad ae af t u p r v w y aa ab ac ad ae af t u vss vdde2 tdi vdd pllcfg1 reset mcko mseo0 mdo3 mdo7 mdo10 mdo13 tck vss vdde2 vdd vss emios5 emios6 vss emios7 pcsa1 vdd pcsa5 vddeh4 vddeh3 pcsb1 pcsb4 pcsa2 vdd vdde2 engclk fr_b_tx emios2 pcsb3 scka souta pcsb0 fr_b_rx pcsa0 pcsa4 emios3 emios0 sckb pcsa3 sinb pcsb5 vddeh3 emios4 emios1 pcsb2 sina soutb vddeh1 pllcfg2 rdy txdb pllcfg0 evti jcomp mseo1 vdde2 mdo1 mdo0 evto mdo5 mdo4 mdo2 vdde2 mdo8 mdo6 mdo11 mdo9 vdd33_2 mdo14 mdo12 vdd tms vss vdde2 vss vss vdde2 vss vss vdde2 vss vdde2 vdde2 vdde2 emios8 emios9 emios10 emios11 12345678910111213 12345678910111213 pxr40 416-ball tepbga (as viewed from top through the package) (3 of 4) vdde2 vdde2 fr_b_ tx_en fr_a_tx fr_a_rx fr_a_ tx_en
pxr40 microcontroller data sheet, rev. 1 pin assignments freescale semiconductor 10 figure 6. pxr40 416-ball tepbga (4 of 4) regctl etpub26 p r v w y aa ab ac ad ae af t u 14 15 16 17 18 19 20 21 22 23 24 25 26 14 15 16 17 18 19 20 21 22 23 24 25 26 pcsc1 vss rxdc pcsc3 vss vdd vddsyn sinc pcsc2 pcsc5 vss vddeh4 txdc vss xtal vddeh5 vdd vddeh6 vddeh5 cnrxd cnrxb sckc cntxd cntxb pcsc0 cnrxc cnrxa soutc cntxc cntxa pcsc4 vdd etpub7 etpub8 etpub9 etpub10 etpub3 etpub4 etpub5 etpub0 etpub1 etpub2 etpub19 etpub20 regsel etpub25 etpub24 etpub23 etpub29 etpub28 etpub27 vdd33_3 etpub30 vsssyn vdd etpub18 etpub17 etpub16 etpub21 etpub22 tcrclkb etpub31 extal vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss emios14 emios15 emios13 emios12 emios18 emios19 emios17 emios16 emios22 emios23 emios21 emios20 emios27 emios26 emios25 emios24 emios31 emios30 emios29 emios28 etpub6 p r v w y aa ab ac ad ae af t u pxr40 416-ba ll tepbga (as viewed from top through the package) (4 of 4) vddreg vssfl
signal properties and muxing pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 11 4 signal properties and muxing table 2 shows the signals properties for each pin on the pxr40. for each port pin that ha s an associated siu_pcr n register to control its pin properties, the supported functions column lists the functions a ssociated with the programming of the siu_pcr n [pa] bit in the order: primary function (p), f unction 2 (f2), function 3 (f3), and gpio (g). see figure 7 . figure 7. supported functions example primary functions secondary functions gpio functions are are listed first are alternate functions listed last gpio/ pcr 1 signal name 2 p/ f/ gfunction 3 function summary i/o pad type 113 tcrclka_irq7_gpio113 p tcrclka etpu a tcr clock i 5v m a1 irq7 external interrupt request i a2 ??? g gpio113 gpio i/o function not implemented on this device table 2. signal properties summary
pxr40 microcontroller data sheet, rev. 1 12 freescale semiconductor table 2. signal properties and muxing summary gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltage 6 state during reset 7 state after reset 8 package location (416) etpu_a 113 tcrclka_irq7_ gpio113 p tcrclka etpu a tcr clock i mh v ddeh1 ?/up ?/up l1 a1 irq7 external interrupt request i a2 ?? ? g gpio113 gpio i/o 114 etpua0_etpua12_ gpio114 p etpua0 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg l2 a1 etpua12 etpu a channel (output only) o a2 ?? ? g gpio114 gpio i/o 115 etpua1_etpua13_ gpio115 p etpua1 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg l3 a1 etpua13 etpu a channel (output only) o a2 ?? ? g gpio115 gpio i/o 116 etpua2_etpua14_ gpio116 p etpua2 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg l4 a1 etpua14 etpu a channel (output only) o a2 ?? ? g gpio116 gpio i/o 117 etpua3_etpua15_ gpio117 p etpua3 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg k1 a1 etpua15 etpu a channel (output only) o a2 ?? ? g gpio117 gpio i/o 118 etpua4_etpua16_ gpio118 p etpua4 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg k2 a1 etpua16 etpu a channel (output only) o a2 ?? ? g gpio118 gpio i/o
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 13 119 etpua5_etpua17_ gpio119 p etpua5 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg k3 a1 etpua17 etpu a channel (output only) o a2 ?? ? g gpio119 gpio i/o 120 etpua6_etpua18_ gpio120 p etpua6 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg k4 a1 etpua18 etpu a channel (output only) o a2 ?? ? g gpio120 gpio i/o 121 etpua7_etpua19_ gpio121 p etpua7 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j1 a1 etpua19 etpu a channel (output only) o a2 ?? ? g gpio121 gpio i/o 122 etpua8_etpua20_ gpio122 p etpua8 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j2 a1 etpua20 etpu a channel (output only) o a2 ?? ? g gpio122 gpio i/o 123 etpua9_etpua21_ gpio123 p etpua9 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j3 a1 etpua21 etpu a channel (output only) o a2 ?? ? g gpio123 gpio i/o 124 etpua10_etpua22_ gpio124 p etpua10 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg j4 a1 etpua22 etpu a channel (output only) o a2 ?? ? g gpio124 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 14 freescale semiconductor 125 etpua11_etpua23_ gpio125 p etpua11 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h1 a1 etpua23 etpu a channel (output only) o a2 ?? ? g gpio125 gpio i/o 126 etpua12_pcsb1_ gpio126 p etpua12 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h2 a1 pcsb1 dspi b peripheral chip select o a2 ?? ? g gpio126 gpio i/o 127 etpua13_pcsb3_ gpio127 p etpua13 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h4 a1 pcsb3 dspi b peripheral chip select o a2 ?? ? g gpio127 gpio i/o 128 etpua14_pcsb4_ gpio128 p etpua14 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg h3 a1 pcsb4 dspi b peripheral chip select o a2 ?? ? g gpio128 gpio i/o 129 etpua15_pcsb5_ gpio129 p etpua15 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g1 a1 pcsb5 dspi b peripheral chip select o a2 ?? ? g gpio129 gpio i/o 130 etpua16_pcsd1_ gpio130 p etpua16 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g2 a1 pcsd1 dspi d peripheral chip select o a2 ?? ? g gpio130 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 15 131 etpua17_pcsd2_ gpio131 p etpua17 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g3 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio131 gpio i/o 132 etpua18_pcsd3_ gpio132 p etpua18 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg g4 a1 pcsd3 dspi d peripheral chip select o a2 ?? ? g gpio132 gpio i/o 133 etpua19_pcsd4_ gpio133 p etpua19 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f1 a1 pcsd4 dspi d peripheral chip select o a2 ?? ? g gpio133 gpio i/o 134 etpua20_irq8_ gpio134 p etpua20 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f2 a1 irq8 external interrupt request i a2 ?? ? g gpio134 gpio i/o 135 etpua21_irq9_ gpio135 p etpua21 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f3 a1 irq9 external interrupt request i a2 ?? ? g gpio135 gpio i/o 136 etpua22_irq10_ gpio136 p etpua22 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg f4 a1 irq10 external interrupt request i a2 ?? ? g gpio136 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 16 freescale semiconductor 137 etpua23_irq11_ gpio137 p etpua23 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e1 a1 irq11 external interrupt request i a2 ?? ? g gpio137 gpio i/o 138 etpua24_irq12_ gpio138 p etpua24 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e2 a1 irq12 external interrupt request i a2 ?? ? g gpio138 gpio i/o 139 etpua25_irq13_ gpio139 p etpua25 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e3 a1 irq13 external interrupt request i a2 ?? ? g gpio139 gpio i/o 140 etpua26_irq14_ gpio140 p etpua26 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg e4 a1 irq14 external interrupt request i a2 ?? ? g gpio140 gpio i/o 141 etpua27_irq15_ gpio141 p etpua27 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg d1 a1 irq15 external interrupt request i a2 ?? ? g gpio141 gpio i/o 142 etpua28_pcsc1_ gpio142 p etpua28 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg d2 a1 pcsc1 dspi c peripheral chip select o a2 ?? ? g gpio142 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 17 143 etpua29_pcsc2_ gpio143 p etpua29 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg d3 a1 pcsc2 dspi c peripheral chip select o a2 ?? ? g gpio143 gpio i/o 144 etpua30_pcsc3_ gpio144 p etpua30 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg c1 a1 pcsc3 dspi c peripheral chip select o a2 ?? ? g gpio144 gpio i/o 145 etpua31_pcsc4_ gpio145 p etpua31 etpu a channel i/o mh v ddeh1 ?/wkpcfg ?/wkpcfg c2 a1 pcsc4 dspi c peripheral chip select o a2 ?? ? g gpio145 gpio i/o etpu_b 146 tcrclkb_irq6_ gpio146 p tcrclkb etpu b tcr clock i mh v ddeh6 ?/up ?/up t23 a1 irq6 external interrupt request i a2 ?? ? g gpio146 gpio i/o 147 etpub0_etpub16_ gpio147 p etpub0 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg t24 a1 etpub16 etpu b channel (output only) o a2 ?? ? g gpio147 gpio i/o 148 etpub1_etpub17_ gpio148 p etpub1 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg t25 a1 etpub17 etpu b channel (output only) o a2 ?? ? g gpio148 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 18 freescale semiconductor 149 etpub2_etpub18_ gpio149 p etpub2 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg t26 a1 etpub18 etpu b channel (output only) o a2 ?? ? g gpio149 gpio i/o 150 etpub3_etpub19_ gpio150 p etpub3 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r23 a1 etpub19 etpu b channel (output only) o a2 ?? ? g gpio150 gpio i/o 151 etpub4_etpub20_ gpio151 p etpub4 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r24 a1 etpub20 etpu b channel (output only) o a2 ?? ? g gpio151 gpio i/o 152 etpub5_etpub21_ gpio152 p etpub5 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r25 a1 etpub21 etpu b channel (output only) o a2 ?? ? g gpio152 gpio i/o 153 etpub6_etpub22_ gpio153 p etpub6 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg r26 a1 etpub22 etpu b channel (output only) o a2 ?? ? g gpio153 gpio i/o 154 etpub7_etpub23_ gpio154 p etpub7 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p23 a1 etpub23 etpu b channel (output only) o a2 ?? ? g gpio154 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 19 155 etpub8_etpub24_ gpio155 p etpub8 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p24 a1 etpub24 etpu b channel (output only) o a2 ?? ? g gpio155 gpio i/o 156 etpub9_etpub25_ gpio156 p etpub9 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p25 a1 etpub25 etpu b channel (output only) o a2 ?? ? g gpio156 gpio i/o 157 etpub10_etpub26_ gpio157 p etpub10 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg p26 a1 etpub26 etpu b channel (output only) o a2 ?? ? g gpio157 gpio i/o 158 etpub11_etpub27_ gpio158 p etpub11 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg n24 a1 etpub27 etpu b channel (output only) o a2 ?? ? g gpio158 gpio i/o 159 etpub12_etpub28_ gpio159 p etpub12 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg n25 a1 etpub28 etpu b channel (output only) o a2 ?? ? g gpio159 gpio i/o 160 etpub13_etpub29_ gpio160 p etpub13 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg n26 a1 etpub29 etpu b channel (output only) o a2 ?? ? g gpio160 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 20 freescale semiconductor 161 etpub14_etpub30_ gpio161 p etpub14 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg m25 a1 etpub30 etpu b channel (output only) o a2 ?? ? g gpio161 gpio i/o 162 etpub15_etpub31_ gpio162 p etpub15 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg m24 a1 etpub31 etpu b channel (output only) o a2 ?? ? g gpio162 gpio i/o 163 etpub16_pcsa1_ gpio163 p etpub16 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u26 a1 pcsa1 dspi a peripheral chip select o a2 ?? ? g gpio163 gpio i/o 164 etpub17_pcsa2_ gpio164 p etpub17 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u25 a1 pcsa2 dspi a peripheral chip select o a2 ?? ? g gpio164 gpio i/o 165 etpub18_pcsa3_ gpio165 p etpub18 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u24 a1 pcsa3 dspi a peripheral chip select o a2 ?? ? g gpio165 gpio i/o 166 etpub19_pcsa4_ gpio166 p etpub19 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg u23 a1 pcsa4 dspi a peripheral chip select o a2 ?? ? g gpio166 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 21 167 etpub20_ gpio167 p etpub20 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg v26 a1 ?? ? a2 ?? ? g gpio167 gpio i/o 168 etpub21_ gpio168 p etpub21 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg v25 a1 ?? ? a2 ?? ? g gpio168 gpio i/o 169 etpub22_ gpio169 p etpub22 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg v24 a1 ?? ? a2 ?? ? g gpio169 gpio i/o 170 etpub23_ gpio170 p etpub23 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg w26 a1 ?? ? a2 ?? ? g gpio170 gpio i/o 171 etpub24_ gpio171 p etpub24 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg w25 a1 ?? ? a2 ?? ? g gpio171 gpio i/o 172 etpub25_ gpio172 p etpub25 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg w24 a1 ?? ? a2 ?? ? g gpio172 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 22 freescale semiconductor 173 etpub26_ gpio173 p etpub26 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg v23 a1 ?? ? a2 ?? ? g gpio173 gpio i/o 174 etpub27_ gpio174 p etpub27 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg y25 a1 ?? ? a2 ?? ? g gpio174 gpio i/o 175 etpub28_ gpio175 p etpub28 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg y24 a1 ?? ? a2 ?? ? g gpio175 gpio i/o 176 etpub29_ gpio176 p etpub29 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg y23 a1 ?? ? a2 ?? ? g gpio176 gpio i/o 177 etpub30_ gpio177 p etpub30 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg aa24 a1 ?? ? a2 ?? ? g gpio177 gpio i/o 178 etpub31_ gpio178 p etpub31 etpu b channel i/o mh v ddeh6 ?/wkpcfg ?/wkpcfg ab24 a1 ?? ? a2 ?? ? g gpio178 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 23 gpio, irq, flexray 440 tcrclkc _ gpio440 9 p ?? ?mhv ddeh7 ?/up ?/up b26 a1 ?? ? a2 ?? ? g gpio440 gpio i/o 441 etpuc0 _ gpio441 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg c25 a1 ?? ? a2 ?? ? g gpio441 gpio i/o 442 etpuc1 _ gpio442 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg c26 a1 ?? ? a2 ?? ? g gpio442 gpio i/o 443 etpuc2 _ gpio443 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg d25 a1 ?? ? a2 ?? ? g gpio443 gpio i/o 444 etpuc3 _ gpio444 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg d26 a1 ?? ? a2 ?? ? g gpio444 gpio i/o 445 etpuc4 _ gpio445 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg e24 a1 ?? ? a2 ?? ? g gpio445 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 24 freescale semiconductor 446 etpuc5 _ gpio446 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg e25 a1 ?? ? a2 ?? ? g gpio446 gpio i/o 447 etpuc6 _ gpio447 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg e26 a1 ?? ? a2 ?? ? g gpio447 gpio i/o 448 etpuc7 _ gpio448 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg f23 a1 ?? ? a2 ?? ? g gpio448 gpio i/o 449 etpuc8 _ gpio449 9 p ? ? i/o mh v ddeh7 ?/wkpcfg ?/wkpcfg f24 a1 ? ? ? a2 ?? ? g gpio449 gpio i/o 450 etpuc9_ irq0_ gpio450 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg f25 a1 irq0 external interrupt request i a2 ?? ? g gpio450 gpio i/o 451 etpuc10_ _irq1_ gpio451 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg f26 a1 irq1 external interrupt request i a2 ?? ? g gpio451 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 25 452 etpuc11_ irq2_ gpio452 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g23 a1 irq2 external interrupt request i a2 ?? ? g gpio452 gpio i/o 453 etpuc12_ irq3_ gpio453 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g24 a1 irq3 external interrupt request i a2 ?? ? g gpio453 gpio i/o 454 etpuc13_ 3_irq4_ gpio454 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g25 a1 irq4 external interrupt request i a2 ?? ? g gpio454 gpio i/o 455 etpuc14_ 4_irq5_ gpio455 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg g26 a1 irq5 external interrupt request i a2 ?? ? g gpio455 gpio i/o 456 etpuc15_ _ gpio456 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h23 a1 ?? ? a2 ?? ? g gpio456 gpio i/o 457 etpuc16_ fr_a_tx_ gpio457 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h24 a1 fr_a_tx flexray a transfer o a2 ?? ? g gpio457 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 26 freescale semiconductor 458 etpuc17_ fr_a_rx_ gpio458 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h25 a1 fr_a_rx flexray a receive i a2 ?? ? g gpio458 gpio i/o 459 etpuc18_ fr_a_tx_en_ gpio459 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg h26 a1 fr_a_tx_en flexray a transfer enable o a2 ?? ? g gpio459 gpio i/o 460 etpuc19_ txda_ gpio460 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j23 a1 txda esci a transmit o a2 ?? ? g gpio460 gpio i/o 461 etpuc20_ rxda _ gpio461 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j24 a1 rxda esci a receive i a2 ?? ? g gpio461 gpio i/o 462 etpuc21_ txdb_ gpio462 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j25 a1 txdb esci b transmit o a2 ?? ? g gpio462 gpio i/o 463 etpuc22_ rxdb_ gpio463 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg j26 a1 rxdb esci b receive i a2 ?? ? g gpio463 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 27 464 etpuc23_ pcsd5_ gpio464 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k23 a1 pcsd5 dspi d peripheral chip select o a2 maa0 adc a mux address 0 o a3 mab0 adc b mux address 0 o g gpio464 gpio i/o 465 etpuc24_ pcsd4_ gpio465 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k24 a1 pcsd4 dspi d peripheral chip select o a2 maa1 adc a mux address 1 o a4 mab1 adc b mux address 1 o g gpio465 gpio i/o 466 etpuc25_ pcsd3_ gpio466 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k25 a1 pcsd3 dspi d peripheral chip select o a2 maa2 adc a mux address 2 o a3 mab2 adc b mux address 2 o g gpio466 gpio i/o 467 etpuc26_ pcsd2_ gpio467 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg k26 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio467 gpio i/o 468 etpuc27_ pcsd1_ gpio468 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg l23 a1 pcsd1 dspi d peripheral chip select o a2 ?? ? g gpio468 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 28 freescale semiconductor 469 etpuc28_ pcsd0_ gpio469 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg l24 a1 pcsd0 dspi d peripheral chip select i/o a2 ?? ? g gpio469 gpio i/o 470 etpuc29_ sckd_ gpio470 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg l25 a1 sckd dspi d clock i/o a2 ?? ? g gpio470 gpio i/o 471 etpuc30_ soutd_ gpio471 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg l26 a1 soutd dspi d data output o a2 ?? ? g gpio471 gpio i/o 472 etpuc31_ sind_ gpio472 9 p ?? ?mhv ddeh7 ?/wkpcfg ?/wkpcfg m23 a1 sind dspi d data input i a2 ?? ? g gpio472 gpio i/o emios 179 emios0_etpua0_ gpio179 p emios0 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae10 a1 etpua0 etpu a channel o a2 ?? ? g gpio179 gpio i/o 180 emios1_etpua1_ gpio180 p emios1 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af10 a1 etpua1 etpu a channel o a2 ?? ? g gpio180 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 29 181 emios2_etpua2_ gpio181 p emios2 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad11 a1 etpua2 etpu a channel o a2 ?? ? g gpio181 gpio i/o 182 emios3_etpua3_ gpio182 p emios3 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae11 a1 etpua3 etpu a channel o a2 ?? ? g gpio182 gpio i/o 183 emios4_etpua4_ gpio183 p emios4 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af11 a1 etpua4 etpu a channel o a2 ?? ? g gpio183 gpio i/o 184 emios5_etpua5_ gpio184 p emios5 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad12 a1 etpua5 etpu a channel o a2 ?? ? g gpio184 gpio i/o 185 emios6_etpua6_ gpio185 p emios6 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae12 a1 etpua6 etpu a channel o a2 ?? ? g gpio185 gpio i/o 186 emios7_etpua7_ gpio186 p emios7 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af12 a1 etpua7 etpu a channel o a2 ?? ? g gpio186 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 30 freescale semiconductor 187 emios8_etpua8_ gpio187 p emios8 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac13 a1 etpua8 etpu a channel o a2 ?? ? g gpio187 gpio i/o 188 emios9_etpua9_ gpio188 p emios9 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad13 a1 etpua9 etpu a channel o a2 ?? ? g gpio188 gpio i/o 189 emios10_sckd_ gpio189 p emios10 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae13 a1 sckd dspi d clock o a2 ?? ? g gpio189 gpio i/o 190 emios11_sind_ gpio190 p emios11 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af13 a1 sind dspi d data input i a2 ?? ? g gpio190 gpio i/o 191 emios12_soutc_ gpio191 p emios12 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg af14 a1 soutc dspi c data output o a2 ?? ? g gpio191 gpio i/o 192 emios13_soutd_ gpio192 p emios13 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae14 a1 soutd dspi d data output o a2 ?? ? g gpio192 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 31 193 emios14_irq0_ gpio193 p emios14 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac14 a1 irq0 external interrupt request i a2 cntxd flexcan d transmit o g gpio193 gpio i/o 194 emios15_irq1_ gpio194 p emios15 emios channel o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad14 a1 irq1 external interrupt request i a2 cnrxd flexcan d receive i g gpio194 gpio i/o 195 emios16_etpub0_ gpio195 p emios16 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af15 a1 etpub0 etpu b channel o a2 fr_dbg[3] flexray debug o g gpio195 gpio i/o 196 emios17_etpub1_ gpio196 p emios17 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae15 a1 etpub1 etpu b channel o a2 fr_dbg[2] flexray debug o g gpio196 gpio i/o 197 emios18_etpub2_ gpio197 p emios18 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac15 a1 etpub2 etpu b channel o a2 fr_dbg[1] flexray debug o g gpio197 gpio i/o 198 emios19_etpub3_ gpio198 p emios19 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad15 a1 etpub3 etpu b channel o a2 fr_dbg[0] flexray debug o g gpio198 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 32 freescale semiconductor 199 emios20_etpub4_ gpio199 p emios20 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af16 a1 etpub4 etpu b channel o a2 ?? ? g gpio199 gpio i/o 200 emios21_etpub5_ gpio200 p emios21 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae16 a1 etpub5 etpu b channel o a2 ?? ? g gpio200 gpio i/o 201 emios22_etpub6_ gpio201 p emios22 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac16 a1 etpub6 etpu b channel o a2 ?? ? g gpio201 gpio i/o 202 emios23_etpub7_ gpio202 p emios23 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad16 a1 etpub7 etpu b channel o a2 ?? ? g gpio202 gpio i/o 203 emios24_pcsb0_ gpio203 p emios24 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af17 a1 pcsb0 dspi b peripheral chip select i/o a2 ?? ? g gpio203 gpio i/o 204 emios25_pcsb1_ gpio204 p emios25 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae17 a1 pcsb1 dspi b peripheral chip select o a2 ?? ? g gpio204 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 33 432 emios26_pcsb2_ gpio432 p emios26 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad17 a1 pcsb2 dspi b peripheral chip select o a2 ?? ? g gpio432 gpio i/o 433 emios27_pcsb3_ gpio433 p emios27 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac17 a1 pcsb3 dspi b peripheral chip select o a2 ?? ? g gpio433 gpio i/o 434 emios28_pcsc0_ gpio434 p emios28 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg af18 a1 pcsc0 dspi c peripheral chip select i/o a2 ?? ? g gpio434 gpio i/o 435 emios29_pcsc1_ gpio435 p emios29 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ae18 a1 pcsc1 dspi c peripheral chip select o a2 ?? ? g gpio435 gpio i/o 436 emios30_pcsc2_ gpio436 p emios30 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ad18 a1 pcsc2 dspi c peripheral chip select o a2 ?? ? g gpio436 gpio i/o 437 emios31_pcsc5_ gpio437 p emios31 emios channel i/o mh v ddeh4 ?/wkpcfg ?/wkpcfg ac18 a1 pcsc5 dspi c peripheral chip select o a2 ?? ? g gpio437 gpio i/o eqadc table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 34 freescale semiconductor ?ana0 p ana0 10 eqadc a analog input i ae/up- down v dda_a1 ana0 ana0 a4 ?ana1 p ana1 10 eqadc a analog input i ae/up- down v dda_a1 ana1 ana1 b5 ?ana2 p ana2 10 eqadc a analog input i ae/up- down v dda_a1 ana2 ana2 c5 ?ana3 p ana3 10 eqadc a analog input i ae/up- down v dda_a1 ana3 ana3 d6 ?ana4 p ana4 10 eqadc a analog input i ae/up- down v dda_a1 ana4 ana4 a5 ?ana5 p ana5 10 eqadc a analog input i ae/up- down v dda_a1 ana5 ana5 b6 ?ana6 p ana6 10 eqadc a analog input i ae/up- down v dda_a1 ana6 ana6 c6 ?ana7 p ana7 10 eqadc a analog input i ae/up- down v dda_a1 ana7 ana7 d7 ?ana8 p ana8 eqadc a analog input i ae v dda_a1 ana8 ana8 a6 ?ana9 p ana9 eqadc a analog input i ae v dda_a1 ana9 ana9 c7 ?ana10 p ana10 eqadc a analog input i ae v dda_a1 ana10 ana10 b7 ?ana11 p ana11 eqadc a analog input i ae v dda_a1 ana11 ana11 a7 ?ana12 p ana12 eqadc a analog input i ae v dda_a1 ana12 ana12 d8 ?ana13 p ana13 eqadc a analog input i ae v dda_a1 ana13 ana13 c8 ?ana14 p ana14 eqadc a analog input i ae v dda_a1 ana14 ana14 b8 ?ana15 p ana15 eqadc a analog input i ae v dda_a1 ana15 ana15 a8 ?ana16 p ana16 eqadc a analog input i ae v dda_a1 ana16 ana16 d9 ?ana17 p ana17 eqadc a analog input i ae v dda_a1 ana17 ana17 c9 ?ana18 p ana18 eqadc a analog input i ae v dda_a1 ana18 ana18 d10 ?ana19 p ana19 eqadc a analog input i ae v dda_a1 ana19 ana19 c10 table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 35 ?ana20 p ana20 eqadc a analog input i ae v dda_a1 ana20 ana20 d11 ?ana21 p ana21 eqadc a analog input i ae v dda_a1 ana21 ana21 c11 ?ana22 p ana22 eqadc a analog input i ae v dda_a1 ana22 ana22 d12 ?ana23 p ana23 eqadc a analog input i ae v dda_a1 ana23 ana23 c12 ?an24 p an24 eqadc a and b shared analog input i ae v dda_a0 an24 an24 b12 ?an25 p an25 eqadc a and b shared analog input i ae v dda_a0 an25 an25 d13 ?an26 p an26 eqadc a and b shared analog input i ae v dda_a0 an26 an26 c13 ?an27 p an27 eqadc a and b shared analog input i ae v dda_a0 an27 an27 b13 ?an28 p an28 eqadc a and b shared analog input i ae v dda_a0 an28 an28 a13 ?an29 p an29 eqadc a and b shared analog input i ae v dda_a0 an29 an29 b14 ?an30 p an30 eqadc a and b shared analog input i ae v dda_b1 an30 an30 c14 ?an31 p an31 eqadc a and b shared analog input i ae v dda_b1 an31 an31 d14 ?an32 p an32 eqadc a and b shared analog input i ae v dda_b1 an32 an32 a14 ?an33 p an33 eqadc a and b shared analog input i ae v dda_b0 an33 an33 b15 ?an34 p an34 eqadc a and b shared analog input i ae v dda_b0 an34 an34 c15 ?an35 p an35 eqadc a and b shared analog input i ae v dda_b0 an35 an35 d15 ?an36 p an36 eqadc a and b shared analog input i ae v dda_b1 an36 an36 a15 ?an37 p an37 eqadc a and b shared analog input i ae v dda_b0 an37 an37 c16 ?an38 p an38 eqadc a and b shared analog input i ae v dda_b0 an38 an38 c17 ?an39 p an39 eqadc a and b shared analog input i ae v dda_b0 an39 an39 d16 ?anb0 p anb0 eqadc b analog input i ae/up- down v dda_b0 anb0 anb0 c18 ?anb1 p anb1 eqadc b analog input i ae/up- down v dda_b0 anb1 anb1 d17 ?anb2 p anb2 eqadc b analog input i ae/up- down v dda_b0 anb2 anb2 d18 table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 36 freescale semiconductor ?anb3 p anb3 eqadc b analog input i ae/up- down v dda_b0 anb3 anb3 d19 ?anb4 p anb4 eqadc b analog input i ae/up- down v dda_b0 anb4 anb4 c19 ?anb5 p anb5 eqadc b analog input i ae/up- down v dda_b0 anb5 anb5 c20 ?anb6 p anb6 eqadc b analog input i ae/up- down v dda_b0 anb6 anb6 b19 ?anb7 p anb7 eqadc b analog input i ae/up- down v dda_b0 anb7 anb7 a20 ?anb8 p anb8 eqadc b analog input i ae v dda_b0 anb8 anb8 b20 ?anb9 p anb9 eqadc b analog input i ae v dda_b0 anb9 anb9 d20 ?anb10 p anb10 eqadc b analog input i ae v dda_b0 anb10 anb10 b21 ?anb11 p anb11 eqadc b analog input i ae v dda_b0 anb11 anb11 a21 ?anb12 p anb12 eqadc b analog input i ae v dda_b0 anb12 anb12 c21 ?anb13 p anb13 eqadc b analog input i ae v dda_b0 anb13 anb13 d21 ?anb14 p anb14 eqadc b analog input i ae v dda_b0 anb14 anb14 a22 ?anb15 p anb15 eqadc b analog input i ae v dda_b0 anb15 anb15 b22 ?anb16 p anb16 eqadc b analog input i ae v dda_b0 anb16 anb16 c22 ?anb17 p anb17 eqadc b analog input i ae v dda_b0 anb17 anb17 a23 ?anb18 p anb18 eqadc b analog input i ae v dda_b0 anb18 anb18 b23 ?anb19 p anb19 eqadc b analog input i ae v dda_b0 anb19 anb19 c23 ?anb20 p anb20 eqadc b analog input i ae v dda_b0 anb20 anb20 d22 ?anb21 p anb21 eqadc b analog input i ae v dda_b0 anb21 anb21 a24 ?anb22 p anb22 eqadc b analog input i ae v dda_b0 anb22 anb22 b24 ?anb23 p anb23 eqadc b analog input i ae v dda_b0 anb23 anb23 a25 ? vrh_a p vrh_a adc a voltage reference high i vddint v rh_a vrh_a vrh_a a12 table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 37 ? vrl_a p vrl_a adc a voltage reference low i vssint v rl_a vrl_a vrl_a a11 ? vrh_b p vrh_b adc b voltage reference high i vddint v rh_b vrh_b vrh_b a19 ? vrl_b p vrl_b adc b voltage reference low i vssint v rl_b vrl_b vrl_b a18 ? refbypcb p refbypcb adc b reference bypass capacitor i ae v dda_b0 refbypcb refbypcb b18 ? refbypca p refbypca adc a reference bypass capacitor i ae v dda_a1 refbypca refbypca b11 ? vdda_a0 p vdda_a internal logic supply input i vdde v dda_a0 vdda_a0 vdda_a0 a9 ? vdda_a1 p vdda_a internal logic supply input i vdde v dda_a1 vdda_a1 vdda_a1 b9 ? refbypca1 p refbypca1 adc a reference bypass capacitor i ae v dda_a1 refbypca1 refbypca1 a10 ? vssa_a1 p vssa_a ground i vsse v ssa_a1 vssa_a1 vssa_a1 b10 ? vdda_b0 p vdda_b internal logic supply input i vdde v dda_b0 vdda_b0 vdda_b0 a16 ? vdda_b1 p vdda_b internal logic supply input i vdde v dda_b1 vdda_b1 vdda_b1 b16 ? vssa_b0 p vssa_b ground i vsse v ssa_b0 vssa_b0 vssa_b0 b17 ? refbypcb1 p refbypcb1 adc b reference bypass capacitor i ae v dda_b0 refbypcb1 refbypcb1 a17 flexray 248 fr_a_tx_ gpio248 p fr_a_tx flexray a transfer o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ad4 a1 ?? ? a2 ?? ? g gpio248 gpio i/o 249 fr_a_rx_ gpio249 p fr_a_rx flexray a receive i fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ae3 a1 ?? ? a2 ?? ? g gpio249 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 38 freescale semiconductor 250 fr_a_tx_en_ gpio250 p fr_a_tx_en flexray a transfer enable o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) af3 a1 ?? ? a2 ?? ? g gpio250 gpio i/o 251 fr_b_tx_ gpio251 p fr_b_tx flexray b transfer o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ad5 a1 ?? ? a2 ?? ? g gpio251 gpio i/o 252 fr_b_rx_ gpio252 p fr_b_rx flexray b receive i fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) ae4 a1 ?? ? a2 ?? ? g gpio252 gpio i/o 253 fr_b_tx_en_ gpio253 p fr_b_tx_en flexray b transfer enable o fs v dde2 ?/up (?/? for rev.1 of the device) ?/up (?/? for rev.1 of the device) af4 a1 ?? ? a2 ?? ? g gpio253 gpio i/o flexcan 83 cntxa_txda_ gpio83 p cntxa flexcan a transmit o mh v ddeh4 ?/up ?/up af19 a1 txda esci a transmit o a2 ?? ? g gpio83 gpio i/o 84 cnrxa_rxda_ gpio84 p cnrxa flexcan a receive i mh v ddeh4 ?/up ?/up ae19 a1 rxda esci a receive i a2 ?? ? g gpio84 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 39 85 cntxb_pcsc3_ gpio85 p cntxb flexcan b transmit o mh v ddeh4 ?/up ?/up ad19 a1 pcsc3 dspi c peripheral chip select o a2 ?? ? g gpio85 gpio i/o 86 cnrxb_pcsc4_ gpio86 p cnrxb flexcan b receive i mh v ddeh4 ?/up ?/up ac19 a1 pcsc4 dspi c peripheral chip select o a2 ?? ? g gpio86 gpio i/o 87 cntxc_pcsd3_ gpio87 p cntxc flexcan c transmit o mh v ddeh4 ?/up ?/up af20 a1 pcsd3 dspi d peripheral chip select o a2 ?? ? g gpio87 gpio i/o 88 cnrxc_pcsd4_ gpio88 p cnrxc flexcan c receive i mh v ddeh4 ?/up ?/up ae20 a1 pcsd4 dspi d peripheral chip select o a2 ?? ? g gpio88 gpio i/o 246 cntxd_ gpio246 p cntxd flexcan d transmit o mh v ddeh4 ?/up ?/up ad20 a1 ?? ? a2 ?? ? g gpio246 gpio i/o 247 cnrxd_ gpio247 p cnrxd flexcan d receive i mh v ddeh4 ?/up ?/up ac20 a1 ?? ? a2 ?? ? g gpio247 gpio i/o esci table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 40 freescale semiconductor 89 txda_ gpio89 p txda esci a transmit o mh v ddeh1 ?/up ?/up m2 a1 ?? ? a2 ?? ? g gpio89 gpio i/o 90 rxda _ gpio90 p rxda esci a receive i mh v ddeh1 ?/up ?/up m3 a1 ?? ? a2 ?? ? g gpio90 gpio i 91 txdb_pcsd1_ gpio91 p txdb esci b transmit o mh v ddeh1 ?/up ?/up p1 a1 pcsd1 dspi d peripheral chip select o a2 ?? ? g gpio91 gpio i/o 92 rxdb_pcsd5_ gpio92 p rxdb esci b receive i mh v ddeh1 ?/up ?/up n1 a1 pcsd5 dspi d peripheral chip select o a2 ?? ? g gpio92 gpio i/o 244 txdc_etrig0_ gpio244 p txdc esci c transmit o mh v ddeh4 ?/up ?/up af23 a1 etrig0 eqadc trigger input i a2 ?? ? g gpio244 gpio i/o 245 rxdc_ gpio245 p rxdc esci c receive i mh v ddeh5 ?/up ?/up ad22 a1 ?? ? a2 ?? ? g gpio245 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 41 dspi 93 scka_pcsc1_ gpio93 p scka dspi a clock i/o mh v ddeh3 ?/up ?/up ad8 a1 pcsc1 dspi c peripheral chip select o a2 ?? ? g gpio93 gpio i/o 94 sina_pcsc2_ gpio94 p sina dspi a data input i mh v ddeh3 ?/up ?/up af7 a1 pcsc2 dspi c peripheral chip select o a2 ?? ? g gpio94 gpio i/o 95 souta_pcsc5_ gpio95 p souta dspi a data output o mh v ddeh3 ?/up ?/up ad7 a1 pcsc5 dspi c peripheral chip select o a2 ?? ? g gpio95 gpio i/o 96 pcsa0_pcsd2_ gpio96 p pcsa0 dspi a peripheral chip select i/o mh v ddeh3 ?/up ?/up ae6 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio96 gpio i/o 97 pcsa1_ gpio97 p pcsa1 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ac6 a1 ?? ? a2 ?? ? g gpio97 gpio i/o 98 pcsa2_ gpio98 p pcsa2 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ac7 a1 ?? ? a2 ?? ? g gpio98 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 42 freescale semiconductor 99 pcsa3_ gpio99 p pcsa3 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ae7 a1 ?? ? a2 ?? ? g gpio99 gpio i/o 100 pcsa4_ gpio100 p pcsa4 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ae5 a1 ?? ? a2 ?? ? g gpio100 gpio i/o 101 pcsa5_etrig1_ gpio101 p pcsa5 dspi a peripheral chip select o mh v ddeh3 ?/up ?/up ad6 a1 etrig1 eqadc trigger input i a2 ?? ? g gpio101 gpio i/o 102 sckb_ gpio102 p sckb dspi b clock i/o mh v ddeh3 ?/up ?/up ae8 a1 ?? ? a2 ?? ? g gpio102 gpio i/o 103 sinb_ gpio103 p sinb dspi b data input i mh v ddeh3 ?/up ?/up ae9 a1 ?? ? a2 ?? ? g gpio103 gpio i/o 104 soutb_ gpio104 p soutb dspi b data output o mh v ddeh3 ?/up ?/up af9 a1 ?? ? a2 ?? ? g gpio104 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 43 105 pcsb0_pcsd2_ gpio105 p pcsb0 dspi b peripheral chip select i/o mh v ddeh3 ?/up ?/up ad9 a1 pcsd2 dspi d peripheral chip select o a2 ?? ? g gpio105 gpio i/o 106 pcsb1_pcsd0_ gpio106 p pcsb1 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ac9 a1 pcsd0 dspi d peripheral chip select i/o a2 ?? ? g gpio106 gpio i/o 107 pcsb2_soutc_ gpio107 p pcsb2 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up af8 a1 soutc dspi c data output o a2 ?? ? g gpio107 gpio i/o 108 pcsb3_sinc_ gpio108 p pcsb3 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ad10 a1 sinc dspi c data input i a2 ?? ? g gpio108 gpio i/o 109 pcsb4_sckc_ gpio109 p pcsb4 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up ac8 a1 sckc dspi c clock i/o a2 ?? ? g gpio109 gpio i/o 110 pcsb5_pcsc0_ gpio110 p pcsb5 dspi b peripheral chip select o mh v ddeh3 ?/up ?/up af6 a1 pcsc0 dspi c peripheral chip select i/o a2 ?? ? g gpio110 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 44 freescale semiconductor 235 sckc_sck_c_lvdsp_ gpio235 p sckc dspi c clock i/o mh+ lvd s v ddeh4 ?/up ?/up ad21 a1 sck_c_lvdsp lvds+ downstream signal positive output clock o a2 ?? ? g gpio235 gpio i/o 236 sinc_sck_c_lvdsm_ gpio236 p sinc dspi c data input i mh+ lvd s v ddeh4 ?/up ?/up ae22 a1 sck_c_lvdsm lvds? downstream signal negative output clock o a2 ?? ? g gpio236 gpio i/o 237 soutc_sout_c_lvdsp_ gpio237 p soutc dspi c data output o mh+ lvd s v ddeh4 ?/up ?/up af21 a1 sout_c_lvdsp lvds+ downstream signal positive output data o a2 ?? ? g gpio237 gpio i/o 238 pcsc0_sout_c_lvdsm_ gpio238 p pcsc0 dspi c peripheral chip select i/o mh+ lvd s v ddeh4 ?/up ?/up ae21 a1 sout_c_lvdsm lvds? downstream signal negative output data o a2 ?? ? g gpio238 gpio i/o 239 pcsc1_ gpio239 p pcsc1 dspi c peripheral chip select o mh v ddeh4 ?/up ?/up ac22 a1 ?? ? a2 ?? ? g gpio239 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 45 240 pcsc2_gpio240 p pcsc2 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ae23 a1 ?? ? a2 ?? ? g gpio240 gpio i/o 241 pcsc3_gpio241 p pcsc3 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ad23 a1 ?? ? a2 ?? ? g gpio241 gpio i/o 242 pcsc4_gpio242 p pcsc4 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up af24 a1 ?? ? a2 ?? ? g gpio242 gpio i/o 243 pcsc5_gpio243 p pcsc5 dspi c peripheral chip select o mh v ddeh5 ?/up ?/up ae24 a1 ?? ? a2 ?? ? g gpio243 gpio i/o reset and clocks ? reset p reset external reset input i mh v ddeh1 reset/up reset/up r2 230 rstout p rstout external reset output o mh v ddeh1 rstout/low rstout/ high a3 212 bootcfg1_irq3_ gpio212 p bootcfg1 boot configuration i mh v ddeh1 bootcfg/ down input/down n2 a1 irq3 external interrupt request i a2 ?? ? g gpio212 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 46 freescale semiconductor 213 wkpcfg_nmi_ gpio213 p wkpcfg weak pull configuration input i mh v ddeh1 wkpcfg/up input/up n3 a1 nmi critical interrupt to core 11 i a2 ?? ? g gpio213 gpio i 208 pllcfg0_irq4_ gpio208 p pllcfg0 fmpll mode configuration input i mh v ddeh1 pllcfg/up input/up r3 a1 irq4 external interrupt request i a2 ?? ? g gpio208 gpio i/o 209 pllcfg1_irq5_ gpio209 p pllcfg1 fmpll mode configuration input i mh v ddeh1 pllcfg/up input/up (for rev2 of the device: ?/up) p2 a1 irq5 external interrupt request i a2 soutd dspi d data output o g gpio209 gpio i/o ? pllcfg2 p pllcfg2 fmpll mode configuration input i mh v ddeh1 pllcfg/ down pllcfg/ down p3 ?xtal p xtal crystal oscillator output o ae v dd33 xtal xtal ac26 ?extal p extal crystal oscillator input i ae v dd33 extal extal ab26 214 engclk p engclk ebi engineering clock output note: extclk (external clock input) selected through siu register) of v dde2 engclk/ enabled engclk/ enabled ad1 jtag and nexus (see footnote 12 about resets) ?evti ? 13 evti nexus event in i f v dde2 ?/up evti/up t4 227 evto (the bam uses this pin to select if auto baud rate is on or off) ? 13 evto nexus event out o f v dde2 abs/up evto/hi u1 219 mcko ? 13 mcko nexus message clock out o f v dde2 o/low disabled 14 t2 table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 47 220 mdo0_gpio220 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo0 15 nexus message data out o f v dde2 o/low mdo0/low u3 a1 ?? ? a2 ?? ? g gpio220 gpio i/o 221 mdo1_gpio221 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo1 15 nexus message data out o f v dde2 o/low ?/down u4 a1 ?? ? a2 ?? ? g gpio221 gpio i/o 222 mdo2_gpio222 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo2 15 nexus message data out o f v dde2 o/low ?/down v1 a1 ?? ? a2 ?? ? g gpio222 gpio i/o 223 mdo3_gpio223 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo3 15 nexus message data out o f v dde2 o/low ?/down v2 a1 ?? ? a2 ?? ? g gpio223 gpio i/o 75 mdo4_gpio75 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo4 15 nexus message data out o f v dde2 o/low ?/down v3 a1 ?? ? a2 ?? ? g gpio75 gpio i/o 76 mdo5_gpio76 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo5 15 nexus message data out o f v dde2 o/low ?/down v4 a1 ?? ? a2 ?? ? g gpio76 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 48 freescale semiconductor 77 mdo6_gpio77 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo6 15 nexus message data out o f v dde2 o/low ?/down w1 a1 ?? ? a2 ?? ? g gpio77 gpio i/o 78 mdo7_gpio78 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo7 15 nexus message data out o f v dde2 o/low ?/down w2 a1 ?? ? a2 ?? ? g gpio78 gpio i/o 79 mdo8_gpio79 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo8 15 nexus message data out o f v dde2 o/low ?/down w3 a1 ?? ? a2 ?? ? g gpio79 gpio i/o 80 mdo9_gpio80 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo9 15 nexus message data out o f v dde2 o/low ?/down y1 a1 ?? ? a2 ?? ? g gpio80 gpio i/o 81 mdo10_gpio81 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo10 15 nexus message data out o f v dde2 o/low ?/down y2 a1 ?? ? a2 ?? ? g gpio81 gpio i/o 82 mdo11_gpio82 (gpio function on this pin is only available on rev.2 of the device) ? 13 mdo11 15 nexus message data out o f v dde2 o/low ?/down y3 a1 ?? ? a2 ?? ? g gpio82 gpio i/o table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 49 231 mdo12_gpio231 ? 13 mdo12 15 nexus message data out o f v dde2 o/low ?/down aa1 a1 ?? ? a2 ?? ? g gpio231 gpio i/o 232 mdo13_gpio232 ? 13 mdo13 15 nexus message data out o f v dde2 o/low ?/down aa2 a1 ?? ? a2 ?? ? g gpio232 gpio i/o 233 mdo14_gpio233 ? 13 mdo14 15 nexus message data out o f v dde2 o/low ?/down aa3 a1 ?? ? a2 ?? ? g gpio233 gpio i/o 234 mdo15_gpio234 ? 13 mdo15 15 nexus message data out o f v dde2 o/low ?/down y4 a1 ?? ? a2 ?? ? g gpio234 gpio i/o 224 mseo0 ? 13 mseo0 15 nexus message start/end out o f v dde2 o/low mseo/hi u2 225 mseo1 ? 13 mseo1 15 nexus message start/end out o f v dde2 o/low mseo/hi t3 226 rdy ? 13 rdy nexus ready output o f v dde2 o/low rdy/hi r4 ?tck ? 13 tck jtag test clock input i f v dde2 tck/down tck/down ab2 ?tdi ? 13 tdi jtag test data input i f v dde2 tdi/up tdi/up ac2 228 tdo ? 13 tdo jtag test data output o f v dde2 tdo/up tdo/up ab1 ?tms ? 13 tms jtag test mode select input i f v dde2 tms/up tms/up ab3 ?jcomp ? 13 jcomp jtag tap controller enable i f v dde2 jcomp/down jcomp/down r1 table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 50 freescale semiconductor ? test ? test test mode select (not for customer use) ifv ddeh1 test/down test/down b4 ? vddsyn ? vddsyn clock synthesizer power input i vdde v ddsyn vddsyn vddsyn ad26 ? vsssyn ? vsssyn clock synthesizer ground input i vsse v ddsyn vsssyn vsssyn aa26 ?vstby ? vstby sram standby power input i vhv v ddeh1 vstby vstby m4 ? regsel ? regsel selects regulator mode (linear/switch mode) iaev ddreg regsel regsel w23 ?regctl ? regctl regulator controller output to base/gate of power transistor o ae v ddreg regctl regctl y26 ?vssfl ? vssfl tie to v ss i vss v ddreg vssfl vssfl ab25 ? vddreg ? vddreg source voltage for on-chip regulators and low voltage detect circuits i vddint v ddreg vddreg vddreg aa25 1 the gpio number is the same as the corresp onding pad configuration register (siu_pcrn) number in pins that have gpio functional ity. for pins that do not have gpio functionality, this number is the pcr number. 2 the primary signal name is used as the pin label on the bga map for identification purposes. however, the primary signal functi on is not available on all devices and is indicated by a dash in the following table columns: signal functions, p/f/g, and i/o type. 3 p/a/g stands for primary/alternate/gpio. this column indicates wh ich function on a pin is primar y, alternate 1, alternate 2, (a lternate n ) and gpio. 4 each line in the function column corresponds to a separate signal function on the pin. for all device i/o pins, the primary, al ternate, or gpio signal functions are designated in the pa field of the siu_p crn registers except where explicitly noted. 5 mh = high voltage, medium speed f = fast speed fs = fast speed with slew ae = analog with esd protection circuitry (up/down = pul l up and pull down circuits included in the pad) vhv = very high voltage 6 vdde (fast i/o) and vddeh (slow i/o) power supply inputs are gro uped into segments. each segment of vddeh pins can connect to a separate 3.3?5.0 v (+5%/?10%) power supply input. each segment of vdde pi ns can connect to a separate 1.8?3.3 v (10%) power supply. 7 the status during reset pin is sampled after the internal por is negated. prior to exiting por, the signal has a high impedance . the terminology used in this column is: o ? output, i ? input, up ? weak pull up enabl ed, down ? weak pulldown enabled, low ? output driven low, high ? output driven high, abs ? auto baud select (during reset or until jcomp assertion). a dash on the left side of the slash denotes that both the input and output buffers for the pin are off. a dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. the signal name to th e left or right of the slash indicates the pin is enabled. 8 the function after reset of a gpi function is general purpose in put. a dash on the left side of the slash denotes that both the input and output buffers for the pin are off. a dash on the right side of the slash denote s that there is no weak pull up/down enabled on the pin. table 2. signal properties and muxing summary (continued) gpio/pcr 1 signal name 2 p/a/g 3 function 4 function summary direction pad type 5 voltag e 6 state during reset 7 state after reset 8 package location (416)
pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 51 9 this signal name includes etpu_c functionality that this device does not have. this is for forward compatibility with devices t hat have an etpu_c. 10 during and just after por negates, internal pull resistors can be enabled, resulting in as much as 4 ma of current draw. the pu ll resistors are disabled when the system clock propagates through the device. 11 nmi does not have a pcr pa configuration; it is enabled when nmi is enabled through the siu_ireer and siu_ifeer registers. 12 nexus reset is different than system reset; mdo 1-11 are enabled when trace (rpm or fpm) is enabled, and mdo 12-15 when fpm tra ce is enabled. mseo and mcko are also dependent on trace (rpm or fpm) being enabled. 13 the nexus pins don?t have a ?primary? function as they are not co nfigured by the siu. the pins are selected by asserting jcomp and configuring the npc. siu values have no effect on the f unction of these pins once enabled. 14 mcko is disabled from reset; it can be enabled from the tool (controlled by nexus npc_pcr register). 15 do not connect pin directly to a power supply or ground.
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 52 5 electrical characteristics this section contains detailed information on power cons iderations, dc/ac electrical ch aracteristics, and ac timing specifications for the pxr40. the electrical specifications are preliminary and are from prev ious designs, design simulations, or initial evaluation. these specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon th ese specifications will be met. finalized speci fications will be published after complete characterization and device qualification s have been completed. 5.1 maximum ratings table 3. absolute maximum ratings 1 spec characteristic symbol min max unit 1 1.2 v core supply voltage v dd ?0.3 2.0 2 v 2 sram standby voltage v stby ?0.3 6.4 3,4 v 3 clock synthesizer voltage v ddsyn ?0.3 5.3 4,5 v 4 i/o supply voltage (i/o buffers and predrivers) v dd33 ?0.3 5.3 4,5 v 5 analog supply voltage (reference to v ssa 6 )v dda 7 ?0.3 6.4 3,4 v 6 i/o supply voltage (fast i/o pads) v dde ?0.3 5.3 4,5 v 7 i/o supply voltage (medium i/o pads) v ddeh ?0.3 6.4 3,4 v 8 voltage regulator input supply voltage v ddreg ?0.3 6.4 3,4 v 9 analog reference high voltage (reference to v rl 8 )v rh 9 ?0.3 6.4 3,4 v 10 v ss to v ssa 8 differential voltage v ss ?v ssa ?0.1 0.1 v 11 v ref differential voltage v rh ?v rl ?0.3 6.4 3,4 v 12 v rl to v ssa differential voltage v rl ?v ssa ?0.3 0.3 v 13 v dd33 to v ddsyn differential voltage v dd33 ?v ddsyn ?0.1 0.1 v 14 v sssyn to v ss differential voltage v sssyn ?v ss ?0.1 0.1 v 15 maximum digital input current 10 (per pin, applies to all digital pins) i maxd ?3 11 3 11 ma 16 maximum analog input current 12 (per pin, applies to all analog pins) i maxa ? 3 7 3 7,11 ma 17 maximum operating temperature range 13 ? die junction temperature t j ?40.0 150.0 o c 18 storage temperature range t stg ?55.0 150.0 o c 19 maximum solder temperature 14 pb-free package snpb package t sdr ? ? 260.0 245.0 o c 20 moisture sensitivity level 15 msl ? 3 ?
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 53 5.2 thermal characteristics 1 functional operating conditions are given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only , and functional operation at the maxima is not guaranteed. stre ss beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 2.0 v for 10 hours cumulative time, 1.32 v +10% for time remaining. 3 6.4 v for 10 hours cumulative time, 5.25 v +10% for time remaining. 4 voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5 5.3 v for 10 hours cumulative time, 3.60 v +10% for time remaining. 6 pxr40 has two analog power supply pins on the pinout: vdda_a and vdda_b. 7 pxr40 has two analog ground supply pins on the pinout: vssa_a and vssa_b. 8 pxr40 has two analog low reference voltage pins on the pinout: vrl_a and vrl_b. 9 pxr40 has two analog high reference voltage pins on the pinout: vrh_a and vrh_b. 10 total injection current for all pins must not exceed 25 ma at maximum operating voltage. 11 injection current of 5 ma allowed for limited duration for anal og (adc) pads and digital 5 v pads. the maximum accumulated time at this current shall be 60 hours. this incl udes an assumption of a 5.25 v maximum analog or v ddeh supply when under this stress condition. 12 total injection current for all analog input pins must not exceed 15 ma. 13 lifetime operation at these specif ication limits is not guaranteed. 14 solder profile per cdf-aec-q100. 15 moisture sensitivity per jedec test method a112. table 4. thermal characteristics, 416-pin tepbga package 1 1 thermal characteristics are targets based on simulation that are subject to change per device characterization. this data is preliminary based on similar package used on other devices. characteristic symbol value unit junction to ambient 2,3 natural convection (single layer board) 2 junction temperature is a function of on-chip po wer dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 3 per jedec jesd51-2 with the single layer board ho rizontal. board meets jesd51-9 specification. r ? ja 24 c/w junction to ambient 2,4 natural convection (four layer board 2s2p) 4 per jedec jesd51-6 with the board horizontal. r ? ja 18 c/w junction to ambient (@200 ft./min., single layer board) r ? jma 19 c/w junction to ambient (@200 ft./min., four layer board 2s2p) r ? jma 14 c/w junction to board 5 5 thermal resistance between the die and the pr inted circuit board per jedec jesd51-8. board temperature is measured on the top su rface of the board near the package. r ? jb 9c/w junction to case 6 6 indicates the average thermal resistance between t he die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. r ? jc 6c/w junction to package top 7 natural convection 7 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. ? jt 2c/w
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 54 5.2.1 general notes for specification s at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from the equation: t j =t a + (r ? ja * p d ) eqn. 1 where: t a = ambient temperature for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the junction to ambient th ermal resistance is an industry st andard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two va lues in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for pack ages such as the tepbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. th e value obtained on the board with the intern al planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the thermal re sistance is expressed as the sum of a junc tion to case thermal resistance and a case to ambient thermal resistance: r ? ja =r ? jc + r ? ca eqn. 2 where: r ? ja = junction to ambient thermal resistance ( o c/w) r ? jc = junction to case thermal resistance ( o c/w) r ? ca = case to ambient thermal resistance ( o c/w) r ? jc is device related and cannot be influenced by the user. the user controls the thermal envi ronment to change the case to ambient thermal resistance, r ? ca . for instance, the user can change the size of th e heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in th e application when heat sink s are not used, the thermal characterization parameter ( ? jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using the following equation: t j =t t + ( ? jt x p d ) eqn. 3 where: t t = thermocouple temperature on top of the package ( o c) ? jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocoup le junction and over about 1 mm. of wire extending from the junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 3081 zanker road
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 55 san jose, ca 95134 (408) 943-6900 mil-spec and eia/jesd (jedec) specifi cations are available from global engi neering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. ? c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedi ngs of semitherm, san diego, 1998, pp. 47-54. ? g. kromann, s. shidore, and s. addison, ?thermal modeling of a pbga for air-cooled applications,? electronic packaging and production, pp. 53-58, march 1998. ? b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of se mitherm, san diego, 1999, pp. 212-220. 5.3 emi (electromagnetic interference) characteristics to find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to www.freescale.com and perform a keyword search for ?radiated emissi ons.? the following tables list the values of the device's radiated emissions operating behaviors. table 5. emc radiated emissions operating behaviors: 416 bga symbol description conditions f osc f sys frequency band (mhz) level (max.) unit notes v re_tem radiated emissions, electric field and magnetic field v dd = 1.2 v v dde = 3.3 v v ddeh = 5 v t a = 25 c 416 bga ebi off clk on fm off 40 mhz crystal 264 mhz (f ebi_cal =66 mhz) 0.15?50 26 db ? v 1 1 determined according to iec standard 61967-2, measuremen t of radiated emissions?tem cell and wideband tem cell method, and sae standard j1752-3, measur ement of radiated emissions from integrated circuits?tem/wideband tem (gtem) cell method. 50?150 30 150?500 34 500?1000 30 iec and sae level i 2 2 i = 36 db ? v ? 1, 3 3 specified according to annex d of iec standard 61967-2, measurement of radiated emissions?tem cell and wideband tem cell method, and appendix d of sae standard j1752-3, measurement of radiated emissions from integrated circuits?tem/wideband tem (gtem) cell method. v re_tem radiated emissions, electric field and magnetic field v dd = 1.2 v v dde = 3.3 v v ddeh = 5 v t a = 25 c 416 bga ebi off clk off fm on 4 4 ?fm on? = fm depth of 2% 40 mhz crystal 264 mhz (f ebi_cal =66 mhz) 0.15?50 24 db ? v 1 50?150 25 150?500 25 500?1000 21 iec and sae level k 5 5 k = 30 db ? v ? 1,3
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 56 5.4 esd characteristics 5.5 pmc/por/lvi electrical specifications note: for adc internal resource measurements, see ta bl e 1 8 in section 5.9.1 adc internal resource measurements . note in the following table, ?unt rimmed? means ?at reset? and ?trimmed? means ?after reset?. table 6. esd ratings 1,2 1 all esd testing is in conformity with cdf-aec-q100 stress test qualificati on for automotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. spec characteristic symbol value unit 1 esd for human body model (hbm) v hbm 2000 v 2 esd for charged device model (cdm) v cdm 750 (corners) 500 (other) v table 7. pmc operating conditions name parameter conditi on min typ max unit note v ddreg supply voltage vddreg 5v nominal ldo5v / smps5v mode 4.5 5 5.5 v 1 1 voltage should be higher than maximum v lv d r e g to avoid lvd event v ddreg supply voltage vddreg 3v nominal ldo3v mode 3.0 3.3 3.6 v 1 v dd33 supply voltage vddsyn / v dd33 3.3v nominal ldo3v mode 3.0 3.3 3.6 v 2 2 applies to both v dd33 (flash supply) and vddsyn (pll supply) pads. voltage should be higher than maximum v lv d 3 3 to avoid lv d eve n t v dd supply voltage vdd 1.2v nominal ? 1.14 1.2 1.32 v 3 3 voltage should be higher than maximum v lv d 1 2 to avoid lvd event table 8. pmc electrical specifications id name parameter min typ max unit 1v bg nominal bandgap reference voltage 0.608 0.620 0.632 v 1a ? untrimmed bandgap reference voltage v bg ? 5% v bg v bg + 5% v 2v dd12out nominal vrc regulated 1.2v output vdd ? 1.2 ? v
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 57 2a ? untrimmed vrc 1.2v output variation before band gap trim (unloaded) note: voltage should be higher than maximum v lv d 1 2 to avoid lvd event v dd12out ? 8% v dd12out v dd12out + 17% v 2b ? trimmed vrc 1.2v out put variation after band gap trim (regctl load max. 20ma, vdd load max. 1a) 1 v dd12out ? 5% v dd12out v dd12out + 10% v 2c v stepv12 trimming step v dd12out ?10?mv 3v porc por rising vdd 1.2v ? 0.7 ? v 3a ? por vdd 1.2v variation v porc ? 30% v porc v porc + 30% 3b ? por 1.2v hysteresis ? 75 ? mv 4v lvd 1 2 nominal rising lvd 1.2v note: ~v dd12out 0.87 ? 1.100 ? v 4a ? untrimmed lvd 1.2v variation before band gap trim note: rising vdd v lv d 1 2 ? 6% v lv d 1 2 v lv d 1 2 + 6% v 4b ? trimmed lvd 1.2v variation after band gap trim rising vdd v lv d 1 2 ? 3% v lv d 1 2 v lv d 1 2 + 3% v 4c ? lvd 1.2v hysteresis 15 20 25 mv 4d v lvdstep12 trimming step lvd 1.2v ? 10 ? mv 5i regctl vrc dc current output on regctl ? ? 20 ma 6 ? voltage regulator 1.2v current consumption vddreg ?3?ma 7v dd33out nominal v reg 3.3v output ? 3.3 ? v 7a ? untrimmed v reg 3.3v output variation before band gap trim (unloaded) note: rising vddsyn v dd33out ? 6% v dd33out v dd33out + 10% v 7b ? trimmed v reg 3.3v output variation after band gap trim (max. load 80ma) v dd33out ? 5% v dd33out v dd33out + 10% v 7c v stepv33 trimming step vddsyn ? 30 ? mv 8v lvd 3 3 nominal rising lvd 3.3v note: ~v dd33out 0.872 ? 2.950 ? v 8a ? untrimmed lvd 3.3v variation before band gap trim note: rising vddsyn v lv d 3 3 ? 5% v lv d 3 3 v lv d 3 3 + 5% v 8b ? trimmed lvd 3.3v variation after bad gap trim note: rising vddsyn v lv d 3 3 ? 3% v lv d 3 3 v lv d 3 3 + 3% v 8c ? lvd 3.3v hysteresis ? 30 ? mv 8d v lvdstep33 trimming step lvd 3.3v ? 30 ? mv table 8. pmc electrical specifications (continued) id name parameter min typ max unit
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 58 9i dd33 v reg = 4.5 v, max dc output current v reg = 4.25 v, max dc output current, crank condition note: max current supplied by vddsyn that does not cause it to drop below v lv d 3 3 ? ? ? ? 80 40 ma ma 10 ? voltage regulator 3.3v current consumption vddreg note: except i dd33 ?2?ma 11 v porreg por rising on vddreg ? 2.00 ? v 11a ? por vddreg variation v porreg ? 30% v porreg v porreg + 30% v 11b ? por vddreg hysteresis ? 250 ? mv 12 v lvd r e g nominal rising lvd vddreg (ldo3v / ldo5v mode) ? 2.950 ? v 12a ? untrimmed lvd vddreg variation before band gap trim note: rising vddreg v lv d r e g ? 5% v lv d r eg v lv d r e g + 5% v 12b ? trimmed lvd vddreg variation after band gap trim note: rising vddreg v lv d r e g ? 3% v lv d r eg v lv d r e g + 3% v 12c ? lvd vddreg hysteresis (ldo3v / ldo5v mode) ?30?mv 12d v lvdstepreg trimming step lvd vddreg (ldo3v / ldo5v mode) ?30?mv 13 v lvd r e g nominal rising lvd vddreg (smps5v mode) ? 4.360 ? v 13a ? untrimmed lvd vddreg variation before band gap trim note: rising vddreg v lv d r e g ? 5% v lv d r eg v lv d r e g + 5% v 13b ? trimmed lvd vddreg variation after band gap trim note: rising vddreg v lv d r e g ? 3% v lv d r eg v lv d r e g + 3% v 13c ? lvd vddreg hysteresis (smps5v mode) ?50?mv 13d v lvdstepreg trimming step lvd vddreg (smps5v mode) ?50?mv 14 v lvda nominal rising lvd vdda ? 4.60 ? v 14a ? untrimmed lvd vdda variation before band gap trim v lv da ? 5% v lv da v lv da + 5% v 14b ? trimmed lvd vdda variation after band gap trim v lv da ? 3% v lv da v lv da + 3% v 14c ? lvd vdda hysteresis ? 150 ? mv table 8. pmc electrical specifications (continued) id name parameter min typ max unit
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 59 5.6 power up/down sequencing there is no power sequencing required among power sources dur ing power up and power down in order to operate within specification as long as the following two rules are met: ? when vddreg is tied to a nominal 3.3v supply, vdd33 and vddsyn must be both shorted to vddreg. ? when vddreg is tied to a 5v supply, vdd33 and vddsyn must be tied together and shall be powered by the internal 3.3v regulator. the recommended power supply behavior is as follows: use 25 v/ millisecond or slower rise time for all supplies. power up each v dde /v ddeh first and then power up v dd . for power down, drop v dd to 0 v first, and then drop all v dde /v ddeh supplies. there is no limit on the fall time for the power supplies. although there are no power up/down sequencing requirements to prevent issues like latch-up, ex cessive current spikes, etc., the state of the i/o pins during power up/down varies according to table 9 and table 10 . 14d v lvdastep trimming step lvd vdda ? 20 ? mv 15 ? smps regulator output resistance note: pullup to vddreg when high, pulldown to vssreg when low. ?1525ohm 16 ? smps regulator clock frequency (after reset) 1.0 1.5 2.4 mhz 17 ? smps regulator overshoot at start-up 2 ?1.321.4v 18 ? smps maximum output current ? 1.0 ? a 19 ? voltage variation on current step 2 (20% to 80% of maximum current with 4 sec constant time) ??0.1v 1 vrc linear regulator is capable of sourcing a current up to 20 ma and sinking a current up to 500 a. when using the recommended ballast transistor the maximum output current provi ded by the voltage regulator vrc/ballast to the vdd core voltage is up to 1a. 2 parameter cannot be tested; this value is based on simulation and characterization. table 9. power sequence pin states for mh and ae pads vdd vdd33 vdde mh pad mh+lvds pads 1 1 mh+lvds pads are output-only. ae/up-down pads high high high normal operation normal operation normal operation ? low high pin is tri-stated (output buffer, input buffer, and weak pulls disabled) outputs driven high pull-ups enabled, pull-downs disabled low high low output low, pin unpowered outputs disabled output low, pin unpowered low high high pin is tri-stated (output buffer, input buffer, and weak pulls disabled) outputs disabled pull-ups enabled, pull-downs disabled table 8. pmc electrical specifications (continued) id name parameter min typ max unit
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 60 5.6.1 power-up if v dde /v ddeh is powered up first, then a threshold de tector tristates all drivers connected to v dde /v ddeh . there is no limit to how long after v dde /v ddeh powers up before v dd must power up. if there are multiple v dde /v ddeh supplies, they can be powered up in any order. for each v dde /v ddeh supply not powered up, the drivers in that v dde /v ddeh segment exhibit the characteristics described in the next paragraph. if v dd is powered up first, then all pads are loaded through the drain diodes to v dde /v ddeh . this presents a heavy load that pulls the pad down to a diode above v ss . current injected by extern al devices connected to the pads must meet the current injection specification. there is no limit to how long after v dd powers up before v dde /v ddeh must power up. the rise times on the power supplies ar e to be no faster than 25 v/millisecond. 5.6.2 power-down if v dd is powered down first, then a ll drivers are tris tated. there is no limit to how long after v dd powers down before v dde /v ddeh must power down. if v dde /v ddeh is powered down first, then all pads are loaded through the drain diodes to v dde /v ddeh . this presents a heavy load that pulls the pad down to a diode above v ss . current injected by exte rnal devices connected to the pads must meet the current injection specificat ion. there is no limit to how long after v dde /v ddeh powers down before v dd must power down. there are no limits on the fall times for the power supplies. 5.6.3 power sequencing and por dependent on v dda during power up or down, v dda can lag other supplies (of magnitude greater than v ddeh /2) within 1 v to prevent any forward-biasing of device di odes that causes leakage cu rrent and/or por. if the voltage difference between v dda and v ddeh is more than 1 v, the following will result: ? triggers por (adc monitors on v ddeh1 segment which powers the reset pin) if the leakage curr ent path created, when v dda is sufficiently low, causes sufficient voltage drop on v ddeh1 node monitored crosses low-voltage detect level. ?if v dda is between 0?2 v, powering all the other segments (especially v ddeh1 ) will not be sufficient to get the part out of reset. ? each v ddeh will have a leakage current to v dda of a magnitude of ((v ddeh ?v dda ? 1 v(diode drop)/200 kohms) up to (v ddeh /2 = v dda +1v). table 10. power sequence pin states for f and fs pads vdd vdd33 vdde f and fs pads low low high outputs drive high low high ? outputs disabled high low low outputs disabled high low high outputs drive high high high low normal operation - except no drive current and input buffer output is unknown. 1 1 the pad pre-drive circuitry will function normally but since vdde is unpowered the outputs will not drive high even though the output pmos can be enabled. high high high normal operation
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 61 ? each v dd has the same behavior; however, the leakage will be small even though there is no current limiting resistor since v dd = 1.32 v max. 5.7 dc electrical specifications table 11. dc electrical specifications spec characteristic symbol min max unit 1 core supply voltage (external regulation) v dd 1.14 1.32 1,2 v 1a core supply voltage (internal regulation) 3 v dd 1.08 1.32 v 2 i/o supply voltage (fast i/o pads) v dde 3.0 3.6 1,4 v 3 i/o supply voltage (medium i/o pads) v ddeh 3.0 5.25 1,5 v 4 3.3 v i/o buffer voltage v dd33 3.0 3.6 1,4 v 5 analog supply voltage v dda 4.75 5.25 1,5 v 6a sram standby voltage keep-out range: 1.2v?2v v stby_low 0.95 6 1.2 v 6b sram standby voltage keep-out range: 1.2v?2v v stby_high 26v 7 voltage regulator control input voltage 7 v ddreg 2.7 8 5.5 1,5 v 8 clock synthesizer operating voltage 9 v ddsyn 3.0 3.6 1,4 v 9 fast i/o input high voltage hysteresis enabled hysteresis disabled v ih_f 0.65 v dde 0.55 v dde v dde +0.3 v 10 fast i/o input low voltage hysteresis enabled hysteresis disabled v il_f v ss ?0.3 0.35 v dde 0.40 v dde v 11 medium i/o input high voltage hysteresis enabled hysteresis disabled v ih_s 0.65 v ddeh 0.55 v ddeh v ddeh +0.3 v 12 medium i/o input low voltage hysteresis enabled hysteresis disabled v il_s v ss ?0.3 0.35 v ddeh 0.40 v ddeh v 13 fast i/o input hysteresis v hys_f 0.1 v dde ?v 14 medium i/o input hysteresis v hys_s 0.1 v ddeh ?v 15 analog input voltage v indc v ssa ?0.1 v dda +0.1 v 16 fast i/o output high voltage 10 v oh_f 0.8 v dde ?v 17 medium i/o output high voltage 11 v oh_s 0.8 v ddeh ?v 18 fast i/o output low voltage 10 v ol_f ?0.2v dde v 19 medium i/o output low voltage 11 v ol_s ?0.2v ddeh v 20 load capacitance (fast i/o) 12 dsc(pcr[8:9]) = 0b00 dsc(pcr[8:9]) = 0b01 dsc(pcr[8:9]) = 0b10 dsc(pcr[8:9]) = 0b11 c l ? ? ? ? 10 20 30 50 pf pf pf pf
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 62 21 input capacitance (digital pins) c in ?7pf 22 input capacitance (analog pins) c in_a ?10pf 24 operating current 1.2 v supplies @ f sys = 264 mhz v dd @1.32 v v stby 13 @1.2 v and 85 o c v stby @6.0 v and 85 o c i dd i ddstby i ddstby6 ? ? ? 1.0 14 0.10 0.15 a ma ma 25 operating current 3.3 v supplies @ f sys = 264 mhz v dd33 15 v ddsyn i dd33 i ddsyn ? ? note 15 7 16 ma ma 26 operating current 5.0 v supplies @ f sys = 264 mhz v dda analog reference supply current (transient) v ddreg i dda i ref i reg ? ? ? 50 17 1.0 22 ma ma ma 27 operating current v dde /v ddeh 18 supplies v dde2 v ddeh1 v ddeh3 v ddeh4 v ddeh5 v ddeh6 v ddeh7 i dd2 i dd1 i dd3 i dd4 i dd5 i dd6 i dd7 ? ? ? ? ? ? ? note 18 ma ma ma ma ma ma ma 28 fast i/o weak pull up/down current 19 3.0 v?3.6 v i act_f 42 158 ? a 29 medium i/o weak pull up/down current 20 3.0 v?3.6 v 4.5 v?5.5 v i act_s 15 35 95 200 ? a ? a 30 i/o input leakage current 21 i inact_d ?2.5 2.5 ? a 31 dc injection current (per pin) i ic ?1.0 1.0 ma 32 analog input current, channel off 22 , an[0:7], an38, an39 analog input current, channel off, all other analog inputs an[x] i inact_a ?250 ?150 250 150 na na 33 v ss differential voltage v ss ?v ssa ?100 100 mv 34 analog reference low voltage v rl v ssa v ssa +100 mv 35 v rl differential voltage v rl ?v ssa ?100 100 mv 36 analog reference high voltage v rh v dda ?100 v dda mv 37 v ref differential voltage v rh ?v rl 4.75 5.25 v 38 v sssyn to v ss differential voltage v sssyn ?v ss ?100 100 mv 39 operating temperature range?ambient (packaged) t a (t l to t h ) ?40.0 125.0 ? c 40 slew rate on power supply pins ? ? 25 v/ms table 11. dc electrical specifications (continued) spec characteristic symbol min max unit
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 63 41 weak pull-up/down resistance 23 , 200 k option r pupd200k 130 280 k ? 42 weak pull-up/down resistance 23 , 100 k option r pupd100k 65 140 k ? 43 weak pull-up/down resistance 23 , 5 k option r pupd5k 1.4 7.5 k ? 44 pull-up/down resistance matching ratios 24 (100k/200k) r pupdmtch ?2.5 +2.5 % 1 voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 2 2.0 v for 10 hours cumulative time, 1.2 v +10% for time remaining. 3 assumed with dc load. 4 5.3 v for 10 hours cumulative time, 3.3 v +10% for time remaining. 5 6.4 v for 10 hours cumulative time, 5.0 v +10% for time remaining. 6 v stby below 0.95 v the ram will not retain states, but will be operational. v stby can be 0 v when bypass standby mode. 7 regulator is functional with derate d performance, with supply voltag e down to 4.0 v for system with v ddreg = 4.5 v (min). 8 2.7 v minimum operating voltage allowed during vehicle crank for system with v ddreg = 3.0 v (min). normal operating voltage should be either v ddreg = 3.0 v (min) or 4.5 v (min) depending on the user regulation voltage system selected. 9 required to be supplied when 3.3 v regulator is disabled. see section 5.5 pmc/por/lvi elec trical specifications. 10 i oh_f = {16,32,47,77} ma and i ol_f = {24,48,71,115} ma for {00,01,10,11} drive mode with v dde = 3.0 v. this spec is for characterization only. 11 i oh_s = {11.6} ma and iol_s = {17.7} ma for {medium} i/o with v dde =4.5v; i oh_s = {5.4} ma and iol_s = {8.1} ma for {medium} i/o with v dde = 3.0 v. these specs are for characterization only. 12 applies to d_clkout, external bus pins, and nexus pins. 13 v stby current specified at 1.0 v at a junction temperature of 85 o c. v stby current is 700 a maximum at a junction temperature of 150 o c. 14 preliminary. specification pending typical an d/or high-use runidd pattern simulation as well as final silicon characterization. 900 ma based on transistor count estimate at wo rst case (wcs) process and temperature condition. 15 power requirements for the v dd33 supply depend on the frequency of operation a nd load of all i/o pins, and the voltages on the i/o segments. see section 5.7.2 i/o pad v dd33 current specifications , for information on both fast (f, fs) and medium (mh) pads. also refer to ta bl e 1 3 for values to calculate power dissipation for specific operation. 16 this value is a target that is subject to change. 17 this value allows a 5 v reference to supply adc + ref. 18 power requirements for each i/o segment depend on the frequency of operation and load of the i/o pins on a particular i/o segment, and the voltage of the i/o segment. see section 5.7.1 i/o pad current specifications , for information on i/o pad power. also refer to ta bl e 1 2 for values to calculate power dissipation for s pecific operation. the total power consumption of an i/o segment is the sum of the individual po wer consumptions for each pin on the segment. 19 absolute value of current, measured at v il and v ih . 20 absolute value of current, measured at v il and v ih . 21 weak pull up/down inactive. measured at v dde = 3.6 v and v ddeh = 5.25 v. applies to pad types f and mh. 22 maximum leakage occurs at maximum operating temperature. leakage current decreases by approximately one-half for each 8to12 o c, in the ambient temperature range of 50 to 125 o c. applies to pad types ae and ae/up-down. see section 4 signal properties and muxing. 23 this programmable option applies only to eqadc differential input channels and is used for biasing and sensor diagnostics 24 pull-up and pull-down resistances are both enabled and settings are equal. table 11. dc electrical specifications (continued) spec characteristic symbol min max unit
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 64 5.7.1 i/o pad current specifications the power consumption of an i/o segment is dependent on th e usage of the pins on a particular segment. the power consumption is the sum of all output pin currents for a particular segment. the output pin current can be calculated from table 12 based on the voltage, frequency, and load on the pin. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 12 . the ac timing of these pads are described in the section 5.11.2 pad ac specifications . 5.7.2 i/o pad v dd33 current specifications the power consumption of the v dd33 supply is dependent on the usage of the pins on all i/o segments. the power consumption is the sum of all input and output pin v dd33 currents for all i/o segments. the v dd33 current draw on fast speed pads can be calculated from table 13 dependent on the voltage, frequency, and load on all f type pins. the v dd33 current draw on medium pads can be calculated from table 13 dependent on voltage and independent on the frequency and load on all mh type pins. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 13 . the ac timing of these pads are described in the section 5.11.2 pad ac specifications . table 12. v dde /v ddeh i/o pad average dc current 1 1 these are average idde numbers for worst case pvt from simulation. currents apply to output pins only. spec pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. voltage (v) drive/slew rate select current (ma) 1medium i drv_mh 50 50 5.25 11 16.0 2 20 505.2501 6.3 3 3.0 50 5.25 00 1.1 4 2.0 200 5.25 00 2.4 5fast i drv_fc 66 10 3.6 00 6.5 666203.6019.4 766303.61010.8 866503.61133.3 9 fast w/ slew control i drv_fsr 66 50 3.6 11 12.0 10 50 50 3.6 10 6.2 11 33.33 50 3.6 01 4.0 12 20 50 3.6 00 2.4 13 20 200 3.6 00 8.9
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 65 5.7.3 lvds pad specifications lvds pads are implemented to support th e msc (microsecond channel) protocol, whic h is an enhanced f eature of the dspi module. table 13. v dd33 pad average dc current 1 1 these are average idde for worst case pvt from simulation . currents apply to output pins only for the fast pads and to input pins only for the medium pads. spec pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. v dd33 (v) v dde (v) drive/slew rate select current (ma) 1mediumi 33_mh ? ? 3.6 5.5 ? 0.0007 2fasti 33_fc 66 10 3.6 3.6 00 0.92 366203.63.6011.14 466303.63.6101.50 566503.63.6112.19 6fast w/ slew control i 33_fsr 66 50 3.6 3.6 11 0.74 750503.63.6100.52 8 33.33 50 3.6 3.6 00 0.19 920503.63.6000.19 10 20 200 3.6 3.6 00 0.19 table 14. dspi lvds pad specification # characteristic symbol condition min. value typ. value max. value unit data rate 1 data frequency f lvdsclk ??50?mhz driver specs 2 differential output voltage v od src=0b00 or 0b11 150 ? 400 mv src=0b01 90 ? 320 src=0b10 160 ? 480 3 common mode voltage (lvds), vos v os ? 1.06 1.2 1.39 v 4 rise/fall time t r /t f ??2?ns 5 propagation delay (low to high) t plh ??4?ns 6 propagation delay (high to low) t phl ??4?ns 7 delay (h/l), sync mode t pdsync ??4?ns 8 delay, z to normal (high/low) t dz ??500?ns
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 66 5.8 oscillator and fmpll electrical characteristics 9 diff skew itphla-tplhbi or itplhb-tphlai t skew ???0.5ns termination 10 trans. line (differential zo) ? ? 95 100 105 ohms 11 temperature ? ? ?40 ? 150 ? c table 15. fmpll electrical specifications 1 (v ddsyn = 3.0 v to 3.6 v, v ss =v sssyn =0v, t a =t l to t h ) 1 all values given are initial design targets and subject to change. spec characteristic symbol min max unit 1 pll reference frequency range 2 (normal mode) crystal reference (pllcfg2 = 0b0) crystal reference (pllcfg2 = 0b1) external reference (pllcfg2 = 0b0) external reference (pllcfg2 = 0b1) 2 crystal and external reference frequency limits depend on device re lying on pll to lock prior to release of reset, default prediv/eprediv, mfd/emfd default se ttings, and vco frequency range. absolute minimum loop frequency is 4 mhz. f ref_crystal f ref_crystal f ref_ext f ref_ext 8 16 8 16 20 40 3 20 40 3 upper tolerance of less than 1% is allowed on 40mhz crystal. mhz 2 loss of reference frequency 4 4 ?loss of reference frequency? is the refer ence frequency detected internally, which transitions the pll into self clocked mode. f lor 100 1000 khz 3 self clocked mode frequency 5 5 self clocked mode frequency is the frequency that the pll operates at when the reference frequency falls below f lor . this frequency is measured at d_clkout. a default rfd value of (0x05) is used in scm mode, and the programmed mfd and rfd values have no effect f scm 416mhz 4 pll lock time 6 t lpll ? < 400 ? s 5 duty cycle of reference 7 t dc 40 60 % 6 frequency un-lock range f ul ?4.0 4.0 % f sys 7 frequency lock range f lck ?2.0 2.0 % f sys 8 d_clkout period jitter 8, 9 measured at f sys max cycle-to-cycle jitter c jitter ?5 5 %f clkout 9 peak-to-peak frequency modulation range limit 10,11 (f sys max must not be exceeded) c mod 04%f sys 10 fm depth tolerance 12 c mod_err ?0.25 0.25 %f sys 11 vco frequency f vco 192 600 mhz 12 modulation rate limits 13 f mod 0.400 1 mhz 13 predivider output frequency range 14 f prediv 410mhz table 14. dspi lvds pad specification (continued)
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 67 6 this specification applies to the period required for the pll to re-lock after changing the mfd frequency control bits in the synthesizer control register (syncr). from power up with crystal o scillator reference, lock time will be additive with crystal startup time. 7 for flexray operation, duty cycle requirements are higher. 8 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered s upplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the cjitter percentage for a given interval. d_clkout divider set to divide-by-2. 9 values are with frequency modulation disabled. if freque ncy modulation is enabled, jitter is the sum of c jitter +c mod . 10 modulation depth selected must not result in f pll value greater than the f pll maximum specified value. 11 maximum and minimum variation from programmed modulation depth is pending characterization. depth settings available in control register are: 2%, 3%, and 4% peak-to-peak. 12 depth tolerance is the programmed modulation depth 0.25% of f sys . violating the vco min/max range may prevent the system from exiting reset. 13 modulation rates less than 400 khz will result in exceedingly long fm calibration durations. modulation rates greater than 1 mhz will result in reduced calibration accuracy. 14 violating this range will cause the vco max/min range to be violated with the default mfd settings out of reset. table 16. oscillator electrical specifications 1 (v ddsyn = 3.0 v to 3.6 v, v ss =v sssyn =0v, t a =t l to t h ) 1 all values given are initial design targets and subject to change. spec characteristic symbol min max unit 1 crystal mode differential amplitude 2 (min differential voltage between extal and xtal) 2 this parameter is meant for those who do not use quartz crystals or resonators, but instead use can oscillators in crystal mode . in that case, v extal ?v xtal ? 400 mv criterion has to be met for oscillat or?s comparator to produce output clock. v crystal_diff_amp | v extal ? v xtal | > 0.4 v ?v 2 crystal mode: internal differential amplifier noise rejection v crystal_diff_amp_nr ? | v extal ? v xtal | < 0.2 v v 3 extal input high voltage bypass mode, external reference v ihext ((v dd33 /2) + 0.4 v) ?v 4 extal input low voltage bypass mode, external reference v ilext ? (v dd33 /2) ? 0.4 v v 5 xtal current 3 3 i xtal is the oscillator bias current out of the xtal pin with both extal and xtal pins grounded. i xtal 13ma 6 total on-chip stray capacitance on xtal c s_xtal ? 1.5 pf 7 total on-chip stray capacitance on extal c s_extal ? 1.5 pf 8 crystal manufacturer?s recommended capacitive load c l see crystal spec see crystal spec pf 9 discrete load capacitance to be connected to extal c l_extal ? (2 c l ?c s_extal ?c pcb_extal 4 ) 4 c pcb_extal and c pcb_xtal are the measured pcb stray capacitances on extal and xtal, respectively. pf 10 discrete load capacitance to be connected to xtal c l_xtal ? (2 c l ?c s_xtal ?c pcb_xtal 4 ) pf
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 68 5.9 eqadc electrical characteristics table 17. eqadc conversion specifications (operating) spec characteristic symbol min max unit 1 adc clock (adclk) frequency f adclk 216mhz 2 conversion cycles single ended conversion cycles 12 bit resolution single ended conversion cycles 10 bit resolution single ended conversion cycles 8 bit resolution note: differential conversion (min) is one clock cycle less than the single-ended conversion values listed here. cc 2+14 2+12 2+10 128 + 14 128 + 12 128 + 10 adclk cycles 3 stop mode recovery time 1 1 stop mode recovery time is the time from the setting of either of the enable bits in the adc control register to the time that the adc is ready to perform conversions. delay from power up to full accuracy = 8 ms. t sr 10 ? ? s 4 resolution 2 2 at v rh ?v rl = 5.12 v, one count = 1.25 mv without using pregain. ?1.25 ? mv 5 inl: 8 mhz adc clock 3 3 inl and dnl are tested from v rl + 50 lsb to v rh ? 50 lsb. the eqadc is guaranteed to be monotonic at 10 bit accuracy (12 bit resolution selected). inl8 ?4 4 4 new design target. actual specification will change following c haracterization. margin for manufacturing has not been fully included. 4 4 lsb 5 5 at v rh ?v rl = 5.12 v, one lsb = 1.25 mv. 6 inl: 16 mhz adc clock 3 inl16 ?8 4 8 4 lsb 7 dnl: 8 mhz adc clock 3 dnl8 ?3 4 3 4 lsb 8 dnl: 16 mhz adc clock 3 dnl16 ?3 4 3 4 lsb 9 offset error without calibration offnc 0 4 100 4 lsb 10 offset error with calibration offwc ?4 4 4 4 lsb 11 full scale gain error without calibration gainnc ?120 4 0 4 lsb 12 full scale gain error with calibration gainwc ?4 4,6 6 the value is valid at 8 mhz, it is 8 counts at 16 mhz. 4 4,6 lsb 13 non-disruptive input injection current 7, 8, 9, 10 7 below disruptive current conditions, the channel being stressed has conversion values of $3ff for analog inputs greater than v rh and $000 for values less than v rl . other channels are not affected by non-disruptive conditions. i inj ?3 3 m ? 14 incremental error due to injection current 11, 12 e inj ?4 4 4 4 counts 15 tue value at 8 mhz 13, 14 (with calibration) tue8 ?4 4,6 4 4,6 counts 16 tue value at 16 mhz 13, 14 (with calibration) tue16 ?8 8 counts 17 maximum differential voltage 15 (danx+ - danx-) or (danx- - danx+) pregain set to 1x setting pregain set to 2x setting pregain set to 4x setting diff max diff max2 diff max4 ? ? ? (v rh ?v rl )/2 (v rh ?v rl )/4 (v rh -v rl )/8 v v v 18 differential input common mode voltage 15 (danx- + danx+)/2 diff cmv (v rh ?v rl )/2 ?5% (v rh ?v rl )/2 +5% v
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 69 5.9.1 adc internal re source measurements 8 exceeding limit may cause conversion error on stressed channels and on unstressed ch annels. transitions within the limit do not affect device reliability or cause permanent damage. 9 input must be current limited to the value specified. to determ ine the value of the required cu rrent-limiting resistor, calcula te resistance values using v posclamp =v dda + 0.5 v and v negclamp = ?0.3 v, then use the larger of the calculated values. 10 condition applies to two adjacent pins at injection limits. 11 performance expected with production silicon. 12 all channels have same 10 k ? pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 70 table 19. standby ram regulator electrical specifications spec characteristic symbol min typ max unit normal mode 1 standby regulator output adc1 channel 194 v adc194 ? 1.2 ? v 2 standby source bias 150 mv to 360 mv (30mv increment @ vref_sel) adc1 channel 195 default value 150 mv (@vref_sel = 1 1 1) v adc195 150 ? 360 mv 3 standby brownout reference adc1 channel 195 v adc195 500 ? 850 mv table 20. adc band gap reference / lvi electrical specifications spec characteristic symbol min typ max unit 1 4.75 lvd (from v dda ) adc1 channel 196 v adc196 ? 4.75 ? v 2 adc bandgap adc0 channel 45 adc1 channel 45 v adc45 1.171 1.220 1.269 v table 21. temperature sensor electrical specifications spec characteristic symbol min typ max unit 1slope ?40 ? c to 100 ? c 1.0 ? c 100 ? c to 150 ? c 1.6 ? c adc0 channel 128 adc1 channel 128 v sadc128 1 1 slope is the measured voltage change per c. ? 5.8 ? mv/ ? c 2 accuracy ?40 ? c to 150 ? c adc0 channel 128 adc1 channel 128 ?? 10.0 ? ? c
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 71 5.10 c90 flash memory electrical characteristics table 24 shows the platform flash co nfiguration register 1 (pfcpr1) settings versus frequency of operation. refer to the device reference manual for definitions of these bit fields. table 22. flash program and erase specifications spec characteristic symbol min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 o c. initial max 2 2 initial factory condition: ? 100 program/erase cycles, 25 o c, typical supply voltage, 80 mhz minimum system frequency. max 3 3 the maximum erase time occurs after the specified number of program/erase cycles. this maximum value is characterized but not guaranteed. unit 1 double word (64 bits) program time 4 4 program times are actual hardware programmin g times and do not include software overhead. t dwprogram ? 38 ? 500 ? s 2 page program time 4,5 5 page size is 128 bits (4 words). t pprogram ? 45 160 500 ? s 3 16 kb block pre-program and erase time t 16kpperase ? 270 1000 5000 ms 4 64 kb block pre-program and erase time t 64kpperase ? 800 1800 5000 ms 5 128 kb block pre-program and erase time t 128kpperase ? 1500 2600 7500 ms 6 256 kb block pre-program and erase time t 256kpperase ? 3000 5200 15000 ms table 23. flash eeprom module life spec characteristic symbol min typical 1 1 typical endurance is evaluated at 25 c. product qualification is performed to the minimum specification. for additional information on the freescale definition of typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . unit 1 number of program/erase cycles per block for 16 kb and 64 kb blocks over the operating temperature range (t j ) p/e 100,000 ? cycles 2 number of program/erase cycles per block for 128 kb and 256 kb blocks over the operating temperature range (t j ) p/e 1,000 100,000 cycles 3 minimum data retention at 85 c ambient temperature 2 blocks with 0?1,000 p/e cycles blocks with 1,001?10,000 p/e cycles blocks with 10,001?1 00,000 p/e cycles 2 ambient temperature averaged over duration of applicat ion, not to exceed product operating temperature range. retention 20 10 5 ? ? ? years
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 72 table 24. pfcpr1 settings vs. frequency of operation 1 1 illegal combinations exist. use entries from the same row in this table. spec clock mode maximum frequency 2 (mhz) 2 this is the nominal maximum frequency of operation: platform runs at f sys /2 in enhanced mode . apc = rwsc wwsc dpfen 3 3 for maximum flash performance, set to 0b1. ipfen 3 pflim 4 4 for maximum flash performance, set to 0b10. bfen 5 5 for maximum flash performance, set to 0b1. core f sys platform f platf 1 enhanced 264 mhz 6 6 this is the nominal maximum frequency of operation in enhanced mode. max speed is the maximum speed allowed including frequency modu lation (fm). 270 mhz parts allow for 264 mhz system core clock(f sys )+2% fm and 132 mhz platform clock (f platf )+ 2% fm. 132 mhz 6 0b011 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 2 enhanced/ full 200 mhz 100 mhz 0b010 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 3 legacy 132 mhz 132 mhz 0b100 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 default setting after reset: 0b111 0b11 0b00 0b00 0b00 0b0
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 73 5.11 ac specifications 5.11.1 clocking figure 8 shows the operating frequency domains of various blocks on pxr40. figure 8. pxr40 block operating frequency domain diagram table 25 shows the operating frequencies of vari ous blocks depending on the device?s clocking mode configuration settings (see table 26 and table 27 for descriptions of bit settings). table 25. pxr40 operating frequencies 1, 2 1 the values in the table are specified at: v dd = 1.02 v to 1.32 v v dde = 3.0 v to 3.6 v v ddeh = 4.5 v to 5.5 v v dd33 and v ddsyn = 3.0 v to 3.6 v t a =t l to t h . mode siu_eccr [ebdf[0:1]] 3 f sys (core) f platf (platform and all blocks except etpu) f etpu (etpu, etpu ram, and ndedi) f ebi_cal 4,5 unit enhanced 01 11 264 264 132 132 132 132 66 33 mhz full 01 11 200 200 100 100 200 200 50 25 mhz legacy 01 11 132 132 132 132 132 132 66 33 mhz pll core platform / etpu / ebi cal bus extal d_clkout f platf note: t cycsys = 1 / f sys t cyc =1 / f platf ?? 2 = divide-by-2 ? x = divide-by-x, depending on siu_sysdiv[bypass] and siu_sysdiv[sysclkdiv]. blocks / (d_clkout is not available on all packages and cannot be programmed for faster than fsys/2.) ? 2 pllcfg[0:1] siu_sysdiv[ sysclkdiv [0:1]] ipg div sel etpu div sel siu_sysdiv[ ipclkdiv [0:1]] f etpu sysdiv ? x flash ndedi div f ebi_cal siu_sysdiv[ bypass ] x = 2, 4, 8, or 16 x=1 f sys siu_eccr[ ebdf [0:1]] f periph
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 74 5.11.2 pad ac specifications 2 up to the maximum frequency rating of the device (refer to ta b l e 3 9 ). the f sys speed is the nominal maximum frequency. 270 mhz parts allow for 264 mhz system clock + 2% fm. 3 see the pxr40 reference manual for full description as not all bit combinations are valid. 4 ebi/calibration bus is not available in all packages. 5 the ebi/calibration bus operating frequency, f ebi_cal , depends on clock divider settings of block?s max allowed frequency of operation. normally f ebi_cal =f platf /2, but can be limited to < f platf /2 in full mode. table 26. ipclkdiv settings siu_sysdiv [ipclkdiv[0:1]] mode description 00 enhanced cpu frequency is doubled (max 264mhz). platform, peripheral, and etpu clocks are 1/2 of cpu frequency 01 full cpu and etpu frequency is doubled (max 200mhz). platform and peripheral clocks are 1/2 of cpu frequency. 10 ? reserved 11 legacy cpu, etpu, platform, and peripheral?s clocks all run at same speed (max 132mhz). table 27. sysclkdiv settings siu_sysdiv [sysclkdiv[0:1]] description 00 divide by 2. 01 divide by 4. 10 divide by 8. 11 divide by 16. table 28. pad ac specifications (v ddeh = 5.0 v, v dde =3.3v) 1 spec pad src/dsc out delay 2,4 l ? h/h ? l (ns) rise/fall 3,4 (ns) load drive (pf) 1medium 5 00 152/165 70/74 50 2 205/220 96/96 200 3 01 28/34 12/15 50 4 52/59 28/31 200 5 11 12/12 5.3/5.9 50 6 32/32 22/22 200
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 75 7fast 6 00 2.5 1.2 10 801 20 910 30 10 11 50 11 fast with slew rate 00 40/40 16/16 50 12 50/50 21/21 200 13 01 13/13 5/5 50 14 19/19 8/8 200 15 10 8/8 2.4/2.4 50 16 12/12 5/5 200 17 11 5/5 1.1/1/1 50 18 8/8 2.6 2.6 19 pull up/down (3.6 v max) ? ? 7500 50 20 pull up/down (5.25 v max) ? 6000 5000/5000 50 1 these are worst case values that are estimated from simulati on and not tested. the values in the table are simulated at v dd = 1.02 v to 1.32 v, v dde = 3.0 v to 3.6 v, v ddeh = 4.75 v to 5.25 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h . 2 this parameter is supplied for reference and is not guaranteed by design and not tested. 3 this parameter is guaranteed by characteriza tion before qualification ra ther than 100% tested. 4 delay and rise/fall are measured to 20% or 80% of the respective signal. 5 out delay is shown in figure 9 . add a maximum of one system cl ock to the output delay for delay with respect to system clock. 6 out delay is shown in figure 9 . add a maximum of one system cl ock to the output delay for delay with respect to system clock. table 29. derated pad ac specifications (v ddeh =3.3v) 1 1 these are worst case values that are es timated from simulation and not tested. th e values in the table are simulated at v dd = 1.08 v to 1.32 v, v dde = 3.0 v to 3.6 v, v ddeh = 3.0 v to 3.6 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h . spec pad src/dsc out delay 2,3 l ? h/h ? l (ns) 2 this parameter is supplied for reference and is not guaranteed by design and not tested. 3 delay and rise/fall are measured to 20% or 80% of the respective signal. rise/fall 4,3 (ns) 4 this parameter is guaranteed by characterizati on before qualification rather than 100% tested. load drive (pf) 1 medium 5 5 out delay is shown in figure 9 . add a maximum of one system clock to the outp ut delay for delay with respect to system clock. 00 200/210 86/86 50 2 270/285 120/120 200 3 01 37/45 15.5/19 50 4 69/82 38/43 200 5 11 18/17 7.6/8.5 50 6 46/49 30/34 200 table 28. pad ac specifications (v ddeh =5.0v, v dde =3.3v) 1 (continued) spec pad src/dsc out delay 2,4 l ? h/h ? l (ns) rise/fall 3,4 (ns) load drive (pf)
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 76 figure 9. pad output delay v dde n / 2 v oh v ol rising edge output delay falling edge output delay pad data input pad output v ddeh n / 2
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 77 5.12 ac timing 5.12.1 generic timing diagrams the generic timing diagrams in figure 10 and figure 11 apply to all i/o pins with pad types f and mh. see 4, signal properties and muxing , for the pad type for each pin. figure 10. generic output delay/hold timing figure 11. generic i nput setup/hold timing v dde / 2 d_clkout a ? maximum output delay time b ? minimum output hold time v dde n / 2 a b i/o outputs v ddeh n / 2 v dde / 2 a b d_clkout v dde n / 2 i/o inputs a ? minimum input se tup time b ? minimum input hold time v ddeh n / 2
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 78 5.12.2 reset and configuration pin timing figure 12. reset and c onfiguration pin timing 5.12.3 ieee 1149.1 interface timing table 30. reset and configuration pin timing 1 1 reset timing specified at: v ddeh = 3.0 v to 5.25 v, v dd = 1.08 v to 1.32 v, t a =t l to t h . spec characteristic symbol min max unit 1 reset pulse width t rpw 10 ? t cyc 2 2 see notes on t cyc on figure 8 and ta bl e 2 5 in section5.11.1clocking . 2 reset glitch detect pulse width t gpw 2?t cyc 2 3 pllcfg, bootcfg, wkpcfg setup time to rstout valid t rcsu 10 ? t cyc 2 4 pllcfg, bootcfg, wkpcfg hold time to rstout valid t rch 0?t cyc 2 table 31. jtag pin ac electrical characteristics 1 spec characteristic symbol min max unit 1 tck cycle time t jcyc 100 ? ns 2 tck clock pulse width (measured at v dde / 2) t jdc 40 60 ns 3 tck rise and fall times (40%?70%) t tckrise ?3ns 4 tms, tdi data setup time t tmss, t tdis 5?ns 5 tms, tdi data hold time t tmsh, t tdih 25 ? ns 6 tck low to tdo data valid t tdov ?10ns 1 2 reset rstout wkpcfg pllcfg 3 4 bootcfg
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 79 figure 13. jtag test clock input timing 7 tck low to tdo data invalid t tdoi 0?ns 8 tck low to tdo high impedance t tdohz ?20ns 9 jcomp assertion time t jcmppw 100 ? ns 10 jcomp setup time to tck low t jcmps 40 ? ns 11 tck falling edge to output valid t bsdv ?50ns 12 tck falling edge to output valid out of high impedance t bsdvz ?50ns 13 tck falling edge to output high impedance t bsdhz ?50ns 14 boundary scan input valid to tck rising edge t bsdst 50 ? ns 15 tck rising edge to boundary scan input invalid t bsdht 50 ? ns 1 jtag timing specified at v dd = 1.08 v to 1.32 v, v dde = 3.0 v to 3.6 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 30 pf with dsc = 0b10, src = 0b00. these specifications apply to jtag boundary scan only. see ta b l e 3 2 for functional specifications. table 31. jtag pin ac electrical characteristics 1 (continued) spec characteristic symbol min max unit tck 1 2 3 3 2
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 80 figure 14. jtag test access port (tap) timing figure 15. jtag jcomp timing tck 4 5 6 7 8 tms, tdi tdo tck jcomp 9 10
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 81 figure 16. jtag boundary scan timing 5.12.4 nexus timing table 32. nexus debug port timing 1 spec characteristic symbol min max unit 1 mcko cycle time t mcyc 2 2 8t cyc 3 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo data valid 4 t mdov ?0.1 0.2 t mcyc 4 mcko low to mseo data valid 4 t mseov ?0.1 0.2 t mcyc 5 mcko low to evto data valid 4 t evtov ?0.1 0.2 t mcyc 6 evti pulse width t evtipw 4.0 ? t tcyc 3 7 evto pulse width t evtopw 1? t mcyc 8 tck cycle time t tcyc 4 5 ?t cyc 3 9 tck duty cycle t tdc 40 60 % tck output signals input signals output signals 11 12 13 14 15
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 82 figure 17. nexus timings 10 tdi, tms data setup time t ntdis, t ntmss 8? ns 11 tdi, tms data hold time t ntdih, t ntmsh 5? ns 12 tck low to tdo data valid t ntdov 010 ns 13 rdy valid to mcko 6 ???? 1 all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 1.08 v to 1.32 v, v dde = 3.0 v to 3.6 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 30 pf with dsc = 0b10. 2 the nexus aux port runs up to 82 mhz (pending characteriza tion). set npc_pcr[mkco_div] to correct division depending on the system frequency, not to exceed maximum nexus aux port frequency. 3 see notes on t cyc on figure 13 and ta bl e 2 5 in section section 5.11.1 clocking . 4 mdo, mseo , and evto data is held valid unt il next mcko low cycle. 5 lower frequency is required to be fully compliant to standard. 6 the rdy pin timing is asynchronous to mcko. the timing is guaranteed by design to function correctly. table 32. nexus debug port timing 1 (continued) spec characteristic symbol min max unit 4 1 2 3 5 mcko mdo mseo evto output data valid 7 evti 6
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 83 figure 18. nexus tck, tdi, tms, tdo timing tdo 10 11 tms, tdi 12 tck 8 9
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 84 5.12.5 external bus interface (ebi) timing table 33. bus operation timing 1 spec characteristic symbol 66 mhz (ext. bus freq) 2 3 unit notes min max 1 d_clkout period t c 15.2 ? ns signals are measured at 50% v dde . 2 d_clkout duty cycle t cdc 45% 55% t c 3 d_clkout rise time t crt ?? 4 ns 4d_clkout fall time t cft ?? 4 ns 5 d_clkout posedge to output signal invalid or high z (hold time) d_add[9:30] d_bdip d_cs[0:3] d_dat[0:15] d_oe d_rd_wr d_ta d_ts d_we [0:3]/d_be [0:3] t coh 1.0/1.5 ? ns hold time selectable via siu_eccr[ebts] bit: ebts = 0: 1.0 ns ebts = 1: 1.5 ns 6 d_clkout posedge to output signal valid (output delay) d_add[9:30] d_bdip d_cs[0:3] d_dat[0:15] d_oe d_rd_wr d_ta d_ts d_we [0:3]/d_be [0:3] t cov ? 7.0/7.5 ns output valid time selectable via siu_eccr[ebts] bit: ebts = 0: 7.0 ns ebts = 1: 7.5 ns
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 85 figure 19. d_clkout timing 7 input signal valid to d_clkout posedge (setup time) d_add[9:30] d_dat[0:15] d_rd_wr d_ta d_ts t cis 5.0/4.5 ? ns input setup time selectable via siu_eccr[ebts] bit: ebts = 0; 5.0ns ebts = 1; 4.5ns 8 d_clkout posedge to input signal invalid (hold time) d_add[9:30] d_dat[0:15] d_rd_wr d_ta d_ts t cih 1.0 ? ns 9 d_ale pulse width t apw 6.5 ? ns the timing is for asynchronous external memory system. 10 d_ale negated to address invalid t aai 2.0/1.0 5 ? ns the timing is for asynchronous external memory system. ale is measured at 50% of vdde. 1 ebi timing specified at v dd = 1.08 v to 1.32 v, v dde = 3.0 v to 3.6 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 30 pf with dsc = 0b10. 2 speed is the nominal maximum frequency. max speed is the maximum speed allowed including frequency modulation (fm). 270 mhz parts allow for 264 mhz system clock + 2% fm. 3 depending on the internal bus speed, set the siu_eccr[ebdf] bi ts correctly not to exceed maximum external bus frequency. the maximum external bus frequency is 66 mhz. 4 refer to fast pad timing in ta b l e 2 8 and ta b l e 2 9 . 5 ale hold time spec is temperature dependant. 1.0 n s spec applies for temperature range -40 to 0 ? c. 2.0 ns spec applies to temperatures > 0 ? c. this spec has no dependency on siu_eccr[ebts] bit. table 33. bus operation timing 1 (continued) spec characteristic symbol 66 mhz (ext. bus freq) 2 3 unit notes min max 1 2 2 3 4 d_clkout v dde / 2 v ol_f v oh_f
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 86 figure 20. synchronous output timing 6 5 5 d_clkout bus 5 output signal output v dde / 2 v dde / 2 v dde / 2 6 5 output signal v dde / 2 6
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 87 figure 21. synchronous input timing figure 22. ale signal timing 7 8 d_clkout input bus 7 8 input signal v dde / 2 v dde / 2 v dde / 2 ipg_clk d_clkout d_ale d_ts addr data d_add/d_dat 9 10
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 88 5.12.6 external interrupt timing (irq pin) figure 23. external interrupt timing 5.12.7 etpu timing table 34. external interrupt timing 1 1 irq timing specified at v dd = 1.08 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h . spec characteristic symbol min max unit 1 irq pulse width low t ipwl 3?t cyc 2 2 see notes on t cyc on figure 8 and ta b l e 2 5 in section 5.11.1 clocking . 2 irq pulse width high t ipwh 3?t cyc 2 3 irq edge to edge time 3 3 applies when irq pins are configured for rising edge or falling edge events, but not both. t icyc 6?t cyc 2 table 35. etpu timing 1 1 etpu timing specified at v dd = 1.08 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 200 pf with src = 0b00. spec characteristic symbol min max unit 1 etpu input channel pulse width t icpw 4?t cyc 2 2 see notes on t cyc on figure 8 and ta b l e 2 5 in section 5.11.1 clocking . 2 etpu output channel pulse width t ocpw 1 3 3 this specification does not include the rise and fall times. wh en calculating the minimum etpu pulse width, include the rise and fall times defined in the slew rate control fiel ds (src) of the pad configuration registers (pcr). ?t cyc 2 irq 1 2 3
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 89 figure 24. etpu timing 5.12.8 emios timing table 36. emios timing 1 1 emios timing specified at v dd = 1.08 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 50 pf with src = 0b00. spec characteristic symbol min max unit 1 emios input pulse width t mipw 4?t cyc 2 2 see notes on t cyc on figure 8 and ta b l e 2 5 in section 5.11.1 clocking . 2 emios output pulse width t mopw 1 3 3 this specification does not include the rise and fall times. wh en calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fiel ds (src) of the pad conf iguration registers (pcr). ?t cyc 2 1 2 etpu output etpu input and tcrclk
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 90 figure 25. emios timing 5.12.9 dspi timing table 37. dspi timing 1 2 spec characteristic symbol peripheral bus freq: 132 mhz unit min max 1 dspi cycle time 3, 4 master (mtfe = 0) slave (mtfe = 0) master (mtfe = 1) slave (mtfe = 1) t sck t sys * 2 t sys *32768*7 ns 2 pcs to sck delay 5 t csc 12 ? ns 3 after sck delay 6 master mode slave mode t asc t sys * 2 t sys *3 ? constraints 7 ? ns 4 sck duty cycle t sdc 0.33 * t sck 0.66 * t sck ns 5 slave access time (ss active to sout valid) t a ? 25 ns 6 slave sout disable time (ss inactive to sout high-z or invalid) t dis ? 25 ns 7pcs x to pcss time t pcsc t sys * 2 t sys * 7 ns 8pcss to pcs x time t pasc t sys * 2 t sys * 7 ns 1 2 emios output emios input
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 91 the dspi in this device can be configured to serialize data to an external device th at implements the microsecond bus protocol. dspi pins support 5 v logic levels or low voltage differential signalling (lvds) for data and clock signals to improve high speed operation. 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 8 master (mtfe = 1, cpha = 1) t sui 20 4 6 20 ? ? ? ? ns ns ns ns 10 data hold ti me for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 8 master (mtfe = 1, cpha = 1) t hi ?3 7 12 ?3 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t suo ? ? ? ? 5 25 13 5 ns ns ns ns 12 data hold ti me for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho ?5 2.5 3 ?5 ? ? ? ? ns ns ns ns 1 dspi timing specified at v dd = 1.08 v to 1.32 v, v ddeh = 3.0 v to 5.5 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, and t a =t l to t h 2 speed is the nominal maximum frequency of platform clock (f platf ). max speed is the maximum speed allowed including frequency modulation (fm). 270 mhz parts allow for 264 mhz for system core clock (f sys ) + 2% fm. 3 the minimum dspi cycle time restricts the baud rate select ion for given system clock rate. these numbers are calculated based on two devices communicating over a dspi link. 4 the actual minimum sck cycle time is limited by pad performance. 5 the maximum value is programmable in dspi_ctar n [pssck] and dspi_ctar n [cssck]. 6 the maximum value is programmable in dspi_ctar n [pasc] and dspi_ctar n [asc]. 7 for example, external master should start sck clock no t earlier than 3 system cloc k periods afte r assertion ss 8 this number is calculated assuming the sm pl_pt bitfield in dspi_mcr is set to 0b10. table 38. dspi lvds timing 1, 2 1 these are typical values that are estimated from simulation. 2 see dspi lvds pad related data in ta b l e 1 4 . characteristic symbol min max unit lvds clock to data/chip select outputs t lv d s data ?0.25 t scyc +0.25 t scyc ns table 37. dspi timing 1 2 (continued) spec characteristic symbol peripheral bus freq: 132 mhz unit min max
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 92 figure 26. dspi classic spi timing ? master, cpha = 0 figure 27. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1)
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 93 figure 28. dspi classic spi timing ? slave, cpha = 0 figure 29. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1)
pxr40 microcontroller data sheet, rev. 1 electrical characteristics freescale semiconductor 94 figure 30. dspi modified transfer format timing ? master, cpha = 0 figure 31. dspi modified transfer format timing ? master, cpha = 1 pcs x 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) pcs x 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1)
electrical characteristics pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 95 figure 32. dspi modified transfer format timing ? slave, cpha = 0 figure 33. dspi modified transfer format timing ? slave, cpha = 1 figure 34. dspi pcs strobe (pcss ) timing last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) pcs x 7 8 pcss
pxr40 microcontroller data sheet, rev. 1 ordering information freescale semiconductor 96 6 ordering information 6.1 orderable parts figure 35 and table 39 describe and list the orderable part numbers for the pxr40. figure 35. pxr40 orderable part number description table 39. pxr40 orderable part number summary part number flash/sram package speed (mhz) mpxr4030vvu264 3 mb / 192 kb 416 pbga (27 mm x 27 mm) 264 mpxr4040vvu264 4 mb / 256 kb 416 pbga (27 mm x 27 mm) 264 mpx 40 note: not all options are available on all devices. see ta bl e 3 9 for more information. r qualification status brand family class flash memory size temperature range v = ?40 c to 105 c operating frequency 1 = 150 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre-qualification (engineering samples) m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow 30 v temperature range vu package identifier 264 r operating frequency tape and reel indicator package identifier vu = 416 pbga 2 = 180 mhz (ambient) family d = display graphics n = connectivity/network r = performance/real time control s=safety flash memory size 30 = 3 mb 40 = 4 mb
package information pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 97 7 package information 7.1 416-pin package the package drawings of the 416-p in tepbga package are shown in figure 36 and figure 37 . figure 36. 416 tepbga package (1 of 2)
pxr40 microcontroller data sheet, rev. 1 package information freescale semiconductor 98 figure 37. 416 tepbga package (2 of 2)
product documentation pxr40 microcontroller data sheet, rev. 1 freescale semiconductor 99 8 product documentation this data sheet is labeled as a particular type: product previe w, advance information, or technical data. definitions of these types are available at: http://www.freescale.com. the following documents are required for a complete description of the device and are necessary to design properly with the parts: ? pxr40 microprocessor reference manual (document number pxr40rm). 9 revision history table 40 describes the changes made to this document between revisions. table 40. revision history revision date description of changes 1 september 2011 initial release: technical data
document number: pxr40 rev. 1 09/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org ? freescale semiconductor, inc. 2011. all rights reserved.

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